JPS5643830A - Logic circuit of low electric power consumption - Google Patents

Logic circuit of low electric power consumption

Info

Publication number
JPS5643830A
JPS5643830A JP11950179A JP11950179A JPS5643830A JP S5643830 A JPS5643830 A JP S5643830A JP 11950179 A JP11950179 A JP 11950179A JP 11950179 A JP11950179 A JP 11950179A JP S5643830 A JPS5643830 A JP S5643830A
Authority
JP
Japan
Prior art keywords
electric power
power consumption
logic circuit
low electric
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11950179A
Other languages
Japanese (ja)
Inventor
Masayuki Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP11950179A priority Critical patent/JPS5643830A/en
Publication of JPS5643830A publication Critical patent/JPS5643830A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

PURPOSE:To prevent a waste of electric current by checking a combination of input bits and then by treating it not as an input to a circuit when the combination does not relate to the output of the digital circuit. CONSTITUTION:When input bits x1, x2, x3, and x4 and phi, 1, 1, and 1 respectively and the output shows ''don't care'', inputting the combination of those inputs holds output 14 at 1 to open the gate of a circuit connected to the next stage, so that it will not be regarded as an input to the circuit.
JP11950179A 1979-09-17 1979-09-17 Logic circuit of low electric power consumption Pending JPS5643830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11950179A JPS5643830A (en) 1979-09-17 1979-09-17 Logic circuit of low electric power consumption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11950179A JPS5643830A (en) 1979-09-17 1979-09-17 Logic circuit of low electric power consumption

Publications (1)

Publication Number Publication Date
JPS5643830A true JPS5643830A (en) 1981-04-22

Family

ID=14762818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11950179A Pending JPS5643830A (en) 1979-09-17 1979-09-17 Logic circuit of low electric power consumption

Country Status (1)

Country Link
JP (1) JPS5643830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0910927A (en) * 1995-06-22 1997-01-14 Chugai Ro Co Ltd Non-flux brazing method in furnace

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0910927A (en) * 1995-06-22 1997-01-14 Chugai Ro Co Ltd Non-flux brazing method in furnace

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