JPS5642336A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5642336A
JPS5642336A JP11826179A JP11826179A JPS5642336A JP S5642336 A JPS5642336 A JP S5642336A JP 11826179 A JP11826179 A JP 11826179A JP 11826179 A JP11826179 A JP 11826179A JP S5642336 A JPS5642336 A JP S5642336A
Authority
JP
Japan
Prior art keywords
layer
psg
cvd method
npcl3
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11826179A
Other languages
English (en)
Japanese (ja)
Other versions
JPS626647B2 (https=
Inventor
Hiroo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11826179A priority Critical patent/JPS5642336A/ja
Publication of JPS5642336A publication Critical patent/JPS5642336A/ja
Publication of JPS626647B2 publication Critical patent/JPS626647B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase

Landscapes

  • Formation Of Insulating Films (AREA)
JP11826179A 1979-09-14 1979-09-14 Manufacturing method of semiconductor device Granted JPS5642336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11826179A JPS5642336A (en) 1979-09-14 1979-09-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11826179A JPS5642336A (en) 1979-09-14 1979-09-14 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5642336A true JPS5642336A (en) 1981-04-20
JPS626647B2 JPS626647B2 (https=) 1987-02-12

Family

ID=14732240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11826179A Granted JPS5642336A (en) 1979-09-14 1979-09-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5642336A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021321A (ja) * 1983-07-12 1985-02-02 Toray Eng Co Ltd 流動層炉による金属物の加熱又は冷却方法
JPS60138974A (ja) * 1983-12-27 1985-07-23 Fuji Electric Corp Res & Dev Ltd 絶縁ゲ−ト型電界効果トランジスタの製造方法
JPS629627A (ja) * 1985-07-06 1987-01-17 Sony Corp 半導体装置の製造方法
JPS6214472A (ja) * 1985-07-12 1987-01-23 Sony Corp 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6021321A (ja) * 1983-07-12 1985-02-02 Toray Eng Co Ltd 流動層炉による金属物の加熱又は冷却方法
JPS60138974A (ja) * 1983-12-27 1985-07-23 Fuji Electric Corp Res & Dev Ltd 絶縁ゲ−ト型電界効果トランジスタの製造方法
JPS629627A (ja) * 1985-07-06 1987-01-17 Sony Corp 半導体装置の製造方法
JPS6214472A (ja) * 1985-07-12 1987-01-23 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS626647B2 (https=) 1987-02-12

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