JPS5635531A - Sampling timing circuit for data - Google Patents

Sampling timing circuit for data

Info

Publication number
JPS5635531A
JPS5635531A JP9371479A JP9371479A JPS5635531A JP S5635531 A JPS5635531 A JP S5635531A JP 9371479 A JP9371479 A JP 9371479A JP 9371479 A JP9371479 A JP 9371479A JP S5635531 A JPS5635531 A JP S5635531A
Authority
JP
Japan
Prior art keywords
output
value
sampling
conversion
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9371479A
Other languages
Japanese (ja)
Other versions
JPS6362923B2 (en
Inventor
Masahide Kondo
Tokio Iguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Original Assignee
Honda Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd filed Critical Honda Motor Co Ltd
Priority to JP9371479A priority Critical patent/JPS5635531A/en
Publication of JPS5635531A publication Critical patent/JPS5635531A/en
Publication of JPS6362923B2 publication Critical patent/JPS6362923B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To secure a high-speed and high-accuracy sampling of the peak value of the measured waveform, by sampling the input waveform periodically for conversion into the digital value and storing and then giving a comparison between the value stored and the output received the digital conversion. CONSTITUTION:The measured input waveform is converted into the digital value through the A/D converter 1 and then read into the memory circuit 3 by the A/D conversion end signal after a fixed time. This action is carried out periodically through the clock pulse oscillator 2. And the memory value B sent from the circuit 3 is always compared with the output A given from the converter 1 at the comparator 6. And the output A is delivered through the terminals 7 and 8 in case the output A is larger and smaller than the value B respectively. The sampling signal generating circuit 9 generates the sampling signal by the output which is obtained when the output A becomes smaller than the value B.
JP9371479A 1979-07-25 1979-07-25 Sampling timing circuit for data Granted JPS5635531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9371479A JPS5635531A (en) 1979-07-25 1979-07-25 Sampling timing circuit for data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9371479A JPS5635531A (en) 1979-07-25 1979-07-25 Sampling timing circuit for data

Publications (2)

Publication Number Publication Date
JPS5635531A true JPS5635531A (en) 1981-04-08
JPS6362923B2 JPS6362923B2 (en) 1988-12-05

Family

ID=14090083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9371479A Granted JPS5635531A (en) 1979-07-25 1979-07-25 Sampling timing circuit for data

Country Status (1)

Country Link
JP (1) JPS5635531A (en)

Also Published As

Publication number Publication date
JPS6362923B2 (en) 1988-12-05

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