SU1478148A1 - Digital meter of amplitude and phase time characteristics - Google Patents

Abstract

The invention relates to the field of radio metering technology and can be used in high-speed measures of the temporal characteristics of amplitude and phase fluctuations of microwave frequency range signals. The aim of the invention is accuracy and enhanced functionality. The goal is achieved by the fact that the digital meter of temporal characteristics of amplitude and phase fluctuations, containing phase detector 4, control unit 10, analog-to-digital converter 7, memory block 8 and calculator 9, additionally includes mixer 1, local oscillator 3, mixer 2, reference oscillator 6 and two triggers 11 and 12. Measurement accuracy is increased by using pulse phase-locked loop with an additional frequency divider to obtain double-quadrature times. 1 il.

Description

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The invention relates to a radio measuring technique and can be used in high-speed measures of the temporal characteristics of fluctuations of the amplitude and phase of the microwave signals, operating in both continuous and pulsed modes.

The purpose of the invention is to improve the accuracy of the fluctuation meter,

The drawing shows a structural diagram of the meter.

The meter contains mixers 1

The D-flip-flop house 11.3 D-flip-flop 11 is connected to a single potential bus.

The digital meter works as follows.

Mixers 1 and 2 convert the high frequency oscillations to a fixed frequency Fnp. In this case, the information on the amplitude and phase of the input signals is proportionally transferred to the oscillations allocated at the outputs of the first and second mixers. The frequency of the reference generator F is four times the value of the prome

and 2, the local oscillator 3, the phase detector 4, 15 the frequency of the frequency (Fnp), since

frequency divider 5, reference generator 6, analog-to-digital converter 7, RAM block 8, calculator 9, control block 10, first and second D-flip-flops 11 and 12. 20

The first input of the mixer 1 is connected to the terminal of the measured input signal, the first input of the mixer 2 is connected to the terminal of the reference input signal. The second inputs of mixers 1 and 2 are connected to the outputs of the local oscillator 3. The input of the local oscillator 3 is connected to the output of the phase detector 4. The output of the reference generator 6 is connected to the triggering input of the analog-digital converter 30, the second input of the control unit 10 and the input of the divider 5, the output of which is connected to the second input of the phase detector 4, the first input of the control unit 10 and to the C input 35 of the D-flip-flop 12, the Second input of the analog-digital converter 7 is connected to the output of the mixer 1 of the measuring channel. The output of the analog-digital converter 7 is connected to the information inputs of the operational memory block 8, the outputs of which are connected to the information inputs of the calculator 9. The second outputs of the calculator 9 are connected to the second control inputs 45 of the operational memory block 8, and the first control outputs the transmitter 9 is connected to the control inputs of the control unit 10. The first control inputs of the operative memory unit 8, / h are connected to the control outputs of the control unit 10. The signal from the first output of the control unit 10 is fed to the R inputs of D-flip-flops 11 and 12. A direct output of D-flip-flop 11 is connected to

The D input of the D flip-flop 12, the output of which is connected to the third input of the control unit 10, the external trigger signal terminal is connected to the C-phase detector 4 and is given a signal (Fon / 4) Fn (s. The triggers 1 1 and 12 provide synchronization of the beginning each implementation with a reference oscillator signal, regardless of the moment when the external start pulse is applied. Thus, it allows several implementations to be averaged. The analog-code converter (ADC) is launched with a period T, TPr / 4, therefore, in one cycle, Fn receive four scores its instantaneous value is not correspondingly

11, U0 + Umsin (P);

ig U0 + Umsin (P + / 2)

 U0 + Umcos (P);

U, U0 + Uwsin (m)

(one)

(2) (3) (4)

 U0 -u sinCP);

U ". U0 + Umsin (P-t-37- / 2)

 U0 - and sobsF),

where and, and are the instantaneous values of the signal;

UM - signal amplitude;

UQ is the constant component of the input signal;

F - phase signal.

I.

The control unit 10, at predetermined time intervals Tg, sends four write pulses to the block, which fix the output ADC codes U and in the memory. P u4. The implementation recorded in the block contains data on the fluctuations of amplitude and phase of the signal.

The calculator 9 determines the amplitude and phase estimates of the signal from the estimates of the instantaneous values of Щ-счит read from block 8. I use the following algorithms for calculating

P ATAN ((U4-U,) / (Ug-U4)). (five

V o.s-Jaj, - and,) g + (W (6

 frequency ratio (Fnp), since

The phase detector 4 is given a signal with a frequency (Fon / 4) Fn (s. Triggers 1 1 and 12 provide synchronization of the start of each implementation with a reference oscillator signal, regardless of when an external trigger pulse is applied. Thus, it is possible to average several implementations. Running the converter 7 analogue code (ADC) occurs with a period T, TPr / 4, therefore, for one oscillation period Fn, four estimates of its instantaneous voltage are obtained, respectively

11, U0 + Umsin (P);

ig U0 + Umsin (P + / 2)

 U0 + Umcos (P);

U, U0 + Uwsin (m)

(one)

(2) (3) (4)

 U0 -u sinCP);

U ". U0 + Umsin (P-t-37- / 2)

 U0 - and sobsF),

where and, and are the instantaneous values of the signal;

UM - signal amplitude;

UQ is the constant component of the input signal;

F - phase signal.

I.

The control unit 10, at predetermined time intervals Tg, generates four write pulses in block 8, which fix the output ADC codes U, and in the memory. P u4. The implementation, recorded in block 8, contains data on fluctuations of the amplitude and phase of the signal.

The calculator 9 determines the amplitude and phase estimates of the signal from the estimated instantaneous values of UC-I read from block 8. The following calculation algorithms are used.

P ATAN ((U4-U,) / (Ug-U4)). (five)

V o.s-Jaj, - and,) g + (W (6)

where Ф, Um - obtained estimates of the phase and amplitude of the signal.

When determining the amplitude and phase according to the formulas (5) and (6), there is no drift of the constant component of the signal for accuracy. The symmetric nonlinearity of the ADC conversion also does not affect the accuracy. The effect of nonlinear distortions of the input signal is significantly weakened.

The control unit 10 (CU) is built on the programmable timer K580VI53.

The control inputs of the CU 10 from the calculator 9 are provided with programming signals that set the operation mode of the timer counters. A number is recorded in the zero counter, meaning the delay of the impulse triggering of external devices in relation to the beginning of the measurement. The first counter of the timer records the number N, meaning the number of implementations. In the second counter, a number is recorded, indicating the length of the pause between samples.

The third input of the CU 10 from the D-flip-flop 12 is given a pulse of the beginning of the measurement. It sets a delay trigger, opens the first Thai counter.

measure, and opens the circuit And inside the JQ control inputs of the operative block

40

10. The delay trigger output opens the timer zero counter and is applied to the second output of the control unit. The second input of the control unit 10 is supplied with clock pulses. At the outputs of the decoder of the control unit, the write signals ZP1-ZP4 are received, which are fed to the first control outputs of the CU. Impulse ЗП4 resets the pause trigger, the signal from the inverse output of this trigger starts the second timer counter. The signal from its direct output blocks the decoder of the control unit. When the second timer counter ends the count, its output pulse restores the pause trigger, the encoder locks-de-- is released, and the next four write pulses ZP1-ZP4 are generated. Further, the pause trigger cycle is repeated.

Block 8 of the RAM is based on the K537RU1 microcircuit. Structurally, it consists of four identical units operating in parallel, which allows increasing the speed. The operation of the blocks in the recording mode is controlled by the write pulses ЗП1-ЗП4, received from the first controllers 50

55

the second outputs of the calculator are connected to the second control inputs of the memory block, characterized in that, in order to increase accuracy, it is equipped with first and second mixers, a local oscillator, a reference generator, a frequency divider, two D-triggers, and the first inputs of the mixers are connected to the terminals of the input signals, the second inputs of the mixers are connected to the first and second outputs of the local oscillator, the input of which is connected to the output of the phase detector, and the first input of the phase detector is connected to the output of the second mixer l, the second input of the phase detector is connected to the output of the frequency divider, to the first input of the control unit and the C input of the second D-trigger, and the input of the frequency divider is connected to the output of the reference oscillator, the second input of the control unit and the trigger input of the analog-digital 1-converter , the second input of the analog-digital converter is connected to the output of the first mixer, the output of the analog-digital converter is connected to the corresponding inputs of the RAM unit, the first ones are controlled

five

0

five

of the control unit's output, the time parameters of the recording mode are formed using timers on K155AGZ chips. The address signals are generated by K155IE5 binary counters. In the read mode, the operation of the memory block 8 controls the computing device by signals from the second control outputs.

The analog + digital converter is built on a K1107PV2 microcircuit, which is an eight-bit ADC of reading type.

A microcomputer of the type DVK-2M is used as a computing device.

Claims (1)

Invention Formula A digital time meter for the amplitude and phase fluctuations, containing a phase detector, a control unit, an analog-to-digital converter, a series-connected main memory unit and a calculator, the first outputs of the control unit being connected to the first 35 40 45 0 five the second outputs of the calculator are connected to the second control inputs of the memory block, characterized in that, in order to increase accuracy, it is equipped with first and second mixers, a local oscillator, a reference generator, a frequency divider, two D-triggers, and the first inputs of the mixers are connected to the terminals of the input signals, the second inputs of the mixers are connected to the first and second outputs of the local oscillator, the input of which is connected to the output of the phase detector, and the first input of the phase detector is connected to the output of the second mixer l, the second input of the phase detector is connected to the output of the frequency divider, to the first input of the control unit and the C input of the second D-trigger, and the input of the frequency divider is connected to the output of the reference oscillator, the second input of the control unit and the trigger input of the analog-digital 1-converter , the second input of the analog-digital converter is connected to the output of the first mixer, the output of the analog-digital converter is connected to the corresponding inputs of the main memory unit, the first controls are 514781486 The calculator outputs are connected with a D-flip-flop, the output of which is connected to the inputs of the control unit to the third input of the control unit, neither, the first output of the control unit and the input of the first D-flip-flop of the wiring is connected to the R-inputs of the first and the keys to the external start terminal, second D-flip-flops, the output of the first D-input of the first D-flip-flop is connected to The D-flip-flop is connected to the D-input by a second single potential bus.