SU1241413A1 - Phase discriminator - Google Patents

Description

1241413

The 1 in QI 1 for the period of the reference matching of the input and reference signal will (will not) be equal to the tree. The goal is achieved by introducing zero. The sign of the voltage and its value DD 5 and the performance of QI 1 on the reversible will determine the sign and value of the counter meter. 4 il.

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The invention relates to radio engineering and can be used in phase locked loop systems to monitor the oscillation phase.

. The purpose of the invention is to develop resistance to resistance.

FIG. 1 shows the structural electrical circuit of the proposed phase discriminator; in fig. 2, 3 and 4 are voltage plots at various points of the phase discriminator circuit under the condition that there are no destabilizing factors: under the condition that the input signal is distorted by interference that shifts a significant moment in the direction of lagging; under the condition that the input signal is distorted by noise, shifting the significant moment in the direction of advance, respectively.

The phase discriminator contains a digital integrator 1, an inverter 2, the first and second elements of AND 3 and 4, a two-threshold detector 5 consisting of a top level comparator 6, a low level comparator 7 and the element OR 8, a clock frequency generator 9.

Phase discriminator works as follows.

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The input signal of the phase distributer, which is a mixture of the useful signal with noise (Fig. 3a) or only the useful signal (Fig. 2a), is fed to the inputs of comparators 6 and 7, the thresholds of which they (and, Uj ) selected in accordance with the level of interference in the communication channel (Fig. 2a, 3a, 4a). The output signals of comparators 6 and 7 are straight angle pulses of various durations, corresponding to the frequency filling of the input signal and the set threshold of operation of the comparators 6 and 7. Since the input signal is

is fed to the non-inverting input of the upper level comparator 6 and to the inverting input of the low level comparator 7, then after the upper level comparator 6, the pulses of the pulses coincide with the polarity of the input signal (Fig. 26, 3b, 46), and the comparator 7 of the lower level Level polarity will be opposite (fig, 2 & Sv, 4c). The positive pulses from the outputs of the comparators 6 and 7 are summed by the element OR 8. As a result of the processing done, the input signal from the continuous signal is converted into a sequence of pulses # characterized by the fact that the zero crossing points that are subject to the maximum interference effect do not participate in the further processing ( fig. 2g, 3g, 4g). The resulting pulse sequence goes to the first inputs of the elements And 3, 4. The second input of the elements And 3 and 4 feeds from the reference Voltage, whose frequency is two times More than the frequency of the input signal (Fig. 2 d, e; 3 d, e; 4 d, e) o H and the third inputs of the elements 3 and 4 are given counting pulses, the frequency of which is: much more than the frequency of the input signal, which determine the accuracy of the phase discriminator (Fig. 2g, 3k, 4g); At the outputs of elements 3 and 4, a burst of pulses is formed, the filling frequency of which corresponds to the frequency of the counting pulses, and the duration — to the relative temporal arrangement of the reference signal pulses and pulses; output element OR (FIG. 2h, and; Зз, and; 4h, and) corresponding to the input signal. From the output of the element And 3 packs of pulses are fed to the summing input of the digital integrator 1, and from the output of the element I 4 - to the subtractive input of the digital

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integrator 1, performed on a reversible counter. If the input and reference signals are in-phase, then the length of the packet, and hence the number of counting pulses in it, arriving at the summing input, will be equal to the length of the stack and the number of counting pulses in it, arriving at the subtracting input of the digital integrator 1 remaining in the digital integrator 1 for the period of the reference voltage will be zero (fig. 2k). The number of count pulses (in fig. 2i, zi, 4i) corresponds to the ordinate of the sawtooth voltage in fig. 2k, 3k, 4k. If the phase of the input signal does not match the phase of the reference signal, then the duration of the bursts of counting pulses fed to the summing and subtracting inputs of the digital integrator 1 will be different. Then the number of pulses remaining in the reversible counter (digital integrator 1) as a result of the described change over the period of the reference voltage will not be zero. The sign of the voltage and its value will determine the sign and the value of pac

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matching input and reference signals.

Claims (1)

Invention Formula A phase discriminator comprising an inverter, two AND elements and a digital integrator, the output of which is the output of the phase discriminator, and the inputs are connected to the corresponding outputs of the AND elements, the first inputs of the AND elements are combined, and the second input of the first And element is the input of the reference signal and is connected via an inverter with a second input of the second element I-, characterized in that, in order to increase the noise immunity, a two-threshold detector is introduced into it, the output of which is connected to the first inputs of the elements And, the information the input is the input of the phase discriminator, and the control inputs are the inputs of the reference voltages, herewith. the digital integrator is designed as a reversible counter, and the third inputs of the And elements are connected to a clock frequency generator.  . UCH.UUU ff G. yf & | X | , rfi.Yr H.i I nig rm TJHJT. LTLTl || I M ixi . t I I t Vut.i (. VNINPI Order Circulation 816 Random polygons pr-tie, Uzhgorod, st. Project, 4 Subscription