JPS5634178A - Readout system of high speed memory - Google Patents

Readout system of high speed memory

Info

Publication number
JPS5634178A
JPS5634178A JP10994079A JP10994079A JPS5634178A JP S5634178 A JPS5634178 A JP S5634178A JP 10994079 A JP10994079 A JP 10994079A JP 10994079 A JP10994079 A JP 10994079A JP S5634178 A JPS5634178 A JP S5634178A
Authority
JP
Japan
Prior art keywords
high speed
address
signal
speed memory
readout signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10994079A
Other languages
Japanese (ja)
Inventor
Toyohisa Teraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10994079A priority Critical patent/JPS5634178A/en
Publication of JPS5634178A publication Critical patent/JPS5634178A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

PURPOSE:To obtain the high speed readout signal by using low speed memory, through the time sharing serial output for the signal read out from a number of memories every given address. CONSTITUTION:RAM1-1, 1-2... are simultaneously accessed every address from the address circuit and the parallel readout signal is serially output via the AND gates 3-1, 3-2... sequentially closed with the time sharing signals 4-1, 4-2... and the OR gate 6. With this architecture, high speed readout signal is obtained by using a number of low speed memories, allowing to form the high resolution TV monitor video signal or the like.
JP10994079A 1979-08-29 1979-08-29 Readout system of high speed memory Pending JPS5634178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10994079A JPS5634178A (en) 1979-08-29 1979-08-29 Readout system of high speed memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10994079A JPS5634178A (en) 1979-08-29 1979-08-29 Readout system of high speed memory

Publications (1)

Publication Number Publication Date
JPS5634178A true JPS5634178A (en) 1981-04-06

Family

ID=14522960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10994079A Pending JPS5634178A (en) 1979-08-29 1979-08-29 Readout system of high speed memory

Country Status (1)

Country Link
JP (1) JPS5634178A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211782A (en) * 1982-06-04 1983-12-09 株式会社日立製作所 Display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58211782A (en) * 1982-06-04 1983-12-09 株式会社日立製作所 Display
JPH0335674B2 (en) * 1982-06-04 1991-05-29 Hitachi Ltd

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