JPS5630738A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5630738A
JPS5630738A JP10701579A JP10701579A JPS5630738A JP S5630738 A JPS5630738 A JP S5630738A JP 10701579 A JP10701579 A JP 10701579A JP 10701579 A JP10701579 A JP 10701579A JP S5630738 A JPS5630738 A JP S5630738A
Authority
JP
Japan
Prior art keywords
film
substrate
oxidized film
coated
oxidized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10701579A
Other languages
Japanese (ja)
Inventor
Hiroyuki Wakabayashi
Naosada Tomari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10701579A priority Critical patent/JPS5630738A/en
Publication of JPS5630738A publication Critical patent/JPS5630738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To make it possible to obtain a surface levelled to a high degree by a method wherein a convex part of an oxidized film is also applied etching at the same time when the oxidized film at a desired portion on a substrate surface is applied etching treatment. CONSTITUTION:A nitriding Si film 12 is formed partially on the surface of the n type Si substrate 11. Then the oxidized film 13 is formed on the surface of the substrate not provided with the film 12. Then again, an oxidized film 20 is formed on the surface of the substrate 11, and a photosensitive material 21 of low viscosity is coated to the surface on which the oxidized film 20 is formed. The material 21 is coated in plenty to the concave part but little to the convex part. Subsequently, by getting rid of the oxidized film at the portion where the material 21 is not coated, soaking the substrate 11 in an etching reagent, the convex part of the film 13 to which the material 21 is little coated is also removed, and therefore, there can be obtained the oxidized film wholly made level. In the following, the material 21 is removed and the film 12 is got rid of. After impurities have been diffused, a p type region 15 is formed within the substrate 11 and further, within the region 15 is formed an n type region 14. Whereby steps such as bird beak of the oxidized film are greatly reduced and wire snappings and the like of the wirings to the electrods can be prevented from the occurrence.
JP10701579A 1979-08-22 1979-08-22 Manufacture of semiconductor device Pending JPS5630738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10701579A JPS5630738A (en) 1979-08-22 1979-08-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10701579A JPS5630738A (en) 1979-08-22 1979-08-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5630738A true JPS5630738A (en) 1981-03-27

Family

ID=14448336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10701579A Pending JPS5630738A (en) 1979-08-22 1979-08-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5630738A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61124150A (en) * 1984-11-20 1986-06-11 Nec Corp Semiconductor integrated circuit device
US5374585A (en) * 1994-05-09 1994-12-20 Motorola, Inc. Process for forming field isolation
US5672538A (en) * 1995-12-04 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd Modified locus isolation process in which surface topology of the locos oxide is smoothed
US5882985A (en) * 1995-10-10 1999-03-16 Advanced Micro Devices, Inc. Reduction of field oxide step height during semiconductor fabrication

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61124150A (en) * 1984-11-20 1986-06-11 Nec Corp Semiconductor integrated circuit device
JPH0584060B2 (en) * 1984-11-20 1993-11-30 Nippon Electric Co
US5374585A (en) * 1994-05-09 1994-12-20 Motorola, Inc. Process for forming field isolation
US5882985A (en) * 1995-10-10 1999-03-16 Advanced Micro Devices, Inc. Reduction of field oxide step height during semiconductor fabrication
US5672538A (en) * 1995-12-04 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd Modified locus isolation process in which surface topology of the locos oxide is smoothed

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