JPS5625300A - Switching controller for memory block - Google Patents

Switching controller for memory block

Info

Publication number
JPS5625300A
JPS5625300A JP10084279A JP10084279A JPS5625300A JP S5625300 A JPS5625300 A JP S5625300A JP 10084279 A JP10084279 A JP 10084279A JP 10084279 A JP10084279 A JP 10084279A JP S5625300 A JPS5625300 A JP S5625300A
Authority
JP
Japan
Prior art keywords
memory block
data
defective
cpu1
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10084279A
Other languages
Japanese (ja)
Inventor
Seijiro Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP10084279A priority Critical patent/JPS5625300A/en
Publication of JPS5625300A publication Critical patent/JPS5625300A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To eliminate limination and burden on an operator in terms of operation by using a substitute memory block automatically once one of memory block becomes defective.
CONSTITUTION: CPU1 reads data out of an assigned memory block of basic memory unit 2 and checks whether a data write error is occurring. When the data error is found, the same data are an assigned address of the same memory block and the data are read out and checked. When the data error is found even in the 2nd data write operation, CPU1 decides that the currently address-assigned memory block of unit 2 is defective. Next, CPU1 exercises automatic switching control over the defective memory block and previously set-up substitute memory 3. Consequently, the address of the defective memory block is used as that of unit 3.
COPYRIGHT: (C)1981,JPO&Japio
JP10084279A 1979-08-08 1979-08-08 Switching controller for memory block Pending JPS5625300A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10084279A JPS5625300A (en) 1979-08-08 1979-08-08 Switching controller for memory block

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10084279A JPS5625300A (en) 1979-08-08 1979-08-08 Switching controller for memory block

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP61062037A Division JPS61286948A (en) 1986-03-19 1986-03-19 Switching controller for memory block

Publications (1)

Publication Number Publication Date
JPS5625300A true JPS5625300A (en) 1981-03-11

Family

ID=14284565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10084279A Pending JPS5625300A (en) 1979-08-08 1979-08-08 Switching controller for memory block

Country Status (1)

Country Link
JP (1) JPS5625300A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208694A (en) * 1981-06-16 1982-12-21 Nippon Telegr & Teleph Corp <Ntt> Switching system of storage cell array

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5189353A (en) * 1975-02-01 1976-08-05
JPS5198927A (en) * 1975-02-26 1976-08-31
JPS51138344A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Memory device
JPS5332A (en) * 1976-06-23 1978-01-05 Fujitsu Ltd Memory redundance system
JPS53136441A (en) * 1977-05-04 1978-11-29 Fujitsu Ltd Memory unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5189353A (en) * 1975-02-01 1976-08-05
JPS5198927A (en) * 1975-02-26 1976-08-31
JPS51138344A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Memory device
JPS5332A (en) * 1976-06-23 1978-01-05 Fujitsu Ltd Memory redundance system
JPS53136441A (en) * 1977-05-04 1978-11-29 Fujitsu Ltd Memory unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208694A (en) * 1981-06-16 1982-12-21 Nippon Telegr & Teleph Corp <Ntt> Switching system of storage cell array

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