JPS61286948A - Switching controller for memory block - Google Patents

Abstract

PURPOSE:To simplify the recognition of a defective memory block and to speed up a replacing work by indicating the defective memory block on the basis of the fused status of a fuse. CONSTITUTION:Under the status that the existence of a defective memory block is set up and stored in a substitute register 81, a CPU 1 specifies memory blocks 20-27 successively and specifies their addresses to control the writing or reading of data. When block specifying addresses A16-A14 are supplied to a decoder 28 and a substitute block detecting circuit 82, a substitute signal BAD is conducted by the detection of coincidence of substitute information C2-Co with block specifying addresses A2-Ao and a decoder 28 inhibits the specification of a memory block 23 on the basis of the block specifying addresses A16-A14 and selects a substitute memory block in stead of the memory block 23.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a memory block switching control device, and more particularly, to a memory block switching control device and a control device for separating a defective memory block from among a plurality of memory blocks and replacing it with a substitute memory device prepared in advance. The present invention relates to a memory block switching control device.

BACKGROUND ART Generally, in various information processing apparatuses, a memory device including a plurality of memory blocks for storing processed data is provided in association with a central processing unit. Conventionally, when a defect occurs in one of a plurality of memory blocks included in a memory device, if the defective memory block is not replaced immediately, desired write data may not be written and stored normally, resulting in information loss. There was a problem that resulted in a processing error.

Therefore, in order to prevent information processing errors from occurring when a defective memory block occurs in one of the memory blocks included in a memory device, an engineer should be on standby at all times and immediately respond to the occurrence of a defective memory block. Memory blocks must be replaced, and labor cannot be saved. In addition, as another method, even if an operator using the information processing apparatus operates with consideration to not using a defective memory block, there is a problem in that the information processing operation is restricted.

<Purpose of the Invention> Therefore, the present invention has been made to solve the above-mentioned problems, and has a configuration in which even if a defective memory block occurs, the defective memory block is automatically switched to an alternative memory device, The alternative information consisting of a bit pattern indicating that there is a defective memory block can be recognized by the blown state of a fuse provided with several bits of the alternative information, so that the defective memory block can be easily recognized at the time of replacement. An object of the present invention is to provide a memory block switching control device.

<Examples> Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating the principle of the invention. In the figure, a central processing unit (hereinafter abbreviated as CPU) I//
i, address bus including address lines of AO-Al1 and D
It is connected to the basic memory device 2 and the alternative memory device 3 via a bidirectional data bus 5 including data lines O to D7 and a clock signal line 7. Further, a control data line 6 for transmitting alternative information is connected between the CPUI and the alternative memory device 3.

The basic memory device 2 has, for example, eight 16-byte memory blocks, and has a total storage capacity of 128-bytes, and is a semiconductor memory (RA).
M) is used. On the other hand, the alternative memory device 3 has a storage capacity (16 bytes) equivalent to at least one memory block included in the basic memory device 2, and uses a semiconductor memory IJ (RA!M). . This alternative memory device 3 is provided as a dedicated memory separate from the basic memory device 2, or is used as a memory block included in the basic memory device 2.

Next, the present invention will be explained in detail with reference to FIG. C
In the normal state, the PU I provides the basic memory device 2 with an address bus for selecting a desired memory block via the address bus 4, and transmits the data to be written to the specified address via the data bus 5, or sends the address to the specified address. Controls reading of data at a specified address. At this time,
The CPU reads data from a designated memory block of the basic memory device 2, and performs a parity check on the read data, for example, to check whether a data write error has occurred. If there is a data error, the CPU writes the same data again to the specified address of the same memory block, then reads and checks the written data, and if a data error is detected in the second data write, the basic memory It is determined that the currently addressed memory block of device 2 is defective.

In this way, when it is determined that there is a defective memory block, the CPU 1 automatically controls switching between the defective memory block and the substitute memory device 3 prepared in advance. As a result, the address of the defective memory block becomes the address of the substitute memory device 3. This memory block switching control is performed by the CPU via the control data line 6.
This is done by setting the address value of the defective memory block in the alternative memory device 3 via the .

Next, the present invention will be described in more detail with reference to specific embodiments.

FIG. 2 is a specific circuit diagram of an embodiment of this invention,
In particular, details of the aforementioned basic memory device 2 and alternative memory device 3 will be shown. In this circuit, attention is focused only on replacing a defective memory block, and circuits specific to RAM used as memory blocks (ie, refresh circuits, etc.) are omitted. In the figure, the basic memory device 2 includes eight memory blocks 20 to 2 with block numbers 0 to 7.
7, and a memory block selection decoder (hereinafter referred to as decoder) 28 which is supplied with 3-bit address lines AI4 to AI6 and derives a signal for selecting a memory block according to the logic state of the 3-bits.

The alternative memory device 3 includes an alternative memory block 30 having a storage capacity of 16 bytes, which is the same as the storage capacity of each memory block 20 to 27 included in the basic memory device 2, and a substitute memory block 30 that can replace a defective memory block when a defective memory block occurs. The memory block 30 is configured to include a switching control means 8 for switching the memory block 30. This switching control means 8 includes an alternative information storage register (hereinafter referred to as an alternative register) 81 that temporarily stores a memory block to be replaced, and the address lines AI4 to
An alternative block detection circuit 32 receives the 3-pit input of A16 and detects which of blocks O to 7 the currently selected memory block is, and a block designation address A.
14-A160 input (this input is designated as AO-A2) and the output CO-C2 (this input is designated as BO-82) representing the defective memory block of the alternate register 8I output are equal (i.e. code A2.AI, AO=82.Bl
.

BO+ (this state is indicated by A=B in the figure) includes an inverter 83 that inverts the no-no level signal derived from the alternative block detection circuit 32 to a low level signal and supplies it to the alternative memory block 30 as a switching command signal.

Note that the memory block 20 included in the basic memory device 2
~27 and alternative memory block 81 are data #DO
It is assumed that a data bus 5 consisting of 8 bits ~D7 and an address line that specifies an address within a memory block using 14 bits AO~A13 of the address bus 4 are commonly connected. Next, The operation of this embodiment will be explained with reference to FIGS. 1 and 2. When power is turned on, the alternative register 81 is cleared by a reset signal (not shown). Then, memory diagnosis is performed at power supply 08 or periodically, and if a memory error is detected, replacement information is set in the replacement register 81. To explain more specifically, for example, when the memory block 23 is defective, the CPU
In the state where memory block 23 is specified by the block specification address (AI4 to A16), AO to AI3
Specify the address in each block with the 14 pits, write the desired write data to the specified address, then read the write data at the address and write the data written first successfully. (parity check, etc.). At this time, if the memory block 23 is defective, the data previously commanded to write and the read data are different, so the CPU sends data C2i indicating that the memory block 23 is defective via the control data line 6. C1it COi, BADi: 0111 is given to the alternative register 81. The signal indicating this memory block defect is the upper 3 bits) (C2i+ C1itC01
=O11) indicates the code (ie, number 3) of the defective memory block 23, and the lower 1 bit of logic ``1'' indicates that there is a defect. Thereafter, the CPUI supplies the clock CP as an acquisition command signal to the substitute register 81, thereby causing the substitute register 81 to read and store a signal indicating that there is a defective memory block (ie, code roI]IJ). In this way, the code of the substitute register 81VCFi and the defective memory block is stored.

As mentioned above, in a state where the alternate register 81 is set and stored to indicate that there is a defective memory block, the CPU
is a plurality of memory blocks 20~ included in the basic memory 2
27 are sequentially designated as blocks and addresses are designated to control data writing or reading. In this operating state, the state in which the memory block 23 is specified, that is, A16
．． When the block designation address of AI5°A14=011 is given to the decoder 28 and the alternative block detection circuit 82, the alternative block detection circuit 82 receives the alternative information (C2°CI, C0=01) which is always given from the alternative register 81.
1) and the block specified address (A2.AI, AO=01
1) Detect that seven matches. By this coincidence detection, the alternative block detection circuit 82 derives an alternative signal (BAD=1+) represented by the lower 1 bit of the alternative register 8I, and the decoder 28 outputs the block specified address (AI6.A15.A14). At the same time, the high level is inverted to low level by an inverter 83 and applied to the alternative memory block 30, and the alternative memory block 30 is selected in place of the memory block 23. Therefore, in a state where the block designation address designates a defective memory block, each address of the alternative memory block 30 is designated by the intra-block addresses A18 to AO that designate each address of the memory block, and Writing or reading is controlled based on the supplied data.

By the way, in the embodiment shown in FIG. 2 described above, the alternative register 8
1 shows a case where a volatile type is used in which substitute information is volatilized at the same time as the power is turned off, but preferably the substitute information needs to be stored and retained until the defective memory block is replaced. Therefore, in such a case, the circuit shown in FIG. 3, which will be described later, may be used.

FIG. 8 is a specific circuit diagram of an alternative storage circuit 81 used in place of the alternative register 81.

In this embodiment, fuses HI-H14 corresponding to the number of bits of the alternative information are provided, and when the alternative information is given, the fuses are blown based on the logical state of the alternative information, and the fuses are blown based on the bit combination of the blown state of the fuse. It stores and holds alternative information. When replacing a defective memory block during maintenance, the defective memory block is known based on the logical state of the blown fuse, and the blown fuse is replaced along with the defective memory block.

Next, a detailed operation will be explained when alternative information is stored and held in the alternative storage circuit 81' of FIG. 3. Normally, each input terminal of the inverter f-14 is connected to a corresponding fuse H1 to
Power supply voltage (+5v i.e. high level) via H4
is supplied, each inverter l-14 has its output C2, CI.

Low level signals are derived as Co and BAD.

At this time, the current flowing through the fuse is selected to be 50 mA or less and does not exceed the rating of the fuse (for example, 2007FIA), so the fuse will not be blown. When input to one of the drivers DRI to DR4 and the capture clock (cp) is applied, each of the drivers DR2 to DR4 derives a high level, and instantaneously increases the current (more than the rated current of the fuse) through the corresponding transistor. For example, a current of 400 mA) is applied to blow out the fuses H2 to H4 corresponding to the logic "1" bit of the alternative information. By blowing fuses H2 to H4, the outputs of inverters 12 to I4 become high level (logic "L"), and the output of inverter 11 becomes low level (logic "0").
Therefore, as a result, the alternative information code ro 1t
IJ will be preserved forever.

As a result, even when the power is cut off, the alternative information representing the defective memory block can be retained, and even after the power is restored, the alternative memory block is automatically used in place of the defective memory block without generating alternative information again. It has the advantage of being able to be controlled to switch.

FIG. 4 is a specific circuit diagram of another embodiment of the present invention, and in particular, in place of the embodiment of FIG.
This shows the case where an alternative memory block is used. In the figure, to explain how this embodiment differs from the embodiment of FIG. 2, the alternative memory device 3 consists of four alternative memory blocks 30-33, blocks AD. In addition, the switching control means 8
//'i, alternative registers 801, 811, 821, 831 corresponding to alternative memory blocks 30 to 33 (!:, alternative information is stored in alternative block detection circuits 802, 812, 822, 832 and alternative registers 801 to 831) When there is a matching output from the decoder 84 and the alternative block detection circuits 812 and 832, which select each alternative register in order to TeA
An OR game (OR game) 85a that gives logic rlJ to the bit, and an OR game (OR game) 85 that derives logic "1" from the B bit based on the coincidence detection outputs of the alternative block detection circuits 322 and 832.
b, alternative block detection circuit 802 and OR game) 8
A NOR gate 85 selects the decoder 86 and inhibits the selection of the decoder 28 in response to the presence of the outputs of 5a and 85b, and four alternative memories based on the 2 bits A and B and the output of the NOR gate 85. and a decoder 86 that selects any one of blocks 30-38.

Since the operation of this embodiment is basically the same as that shown in FIG. 2, the operations different from those shown in FIG. 2 will be briefly explained. For example, assuming that the memory block 23 included in the basic memory device 2 is defective, the CPU
2i, C1i, COi.

BADi) to each alternative register 801, 811゜821
．． Commonly given to 831. At the same time, CPU1f
f A 2-bit address specifying an alternative memory block to be substituted for the defective memory block 23 is derived and given to the decoder 84. When switching the substitute memory block 30 to replace the defective memory block 28, a 2-bit code "00" is given to the decoder 84 as an address for selecting the substitute register. In response, decoder 84 provides a capture signal (cp) to alternative register 801 to select alternative register 801 corresponding to code "00" from among four alternative registers 801-881. For this reason,
Alternative register 801 is alternative information (code r01+1J)
It takes in and stores it, and provides its output to the alternative block detection circuit 802.

As mentioned above, when the CPU derives the block designation address (011) and designates the memory block 23 while the replacement information is stored and held in the replacement register 801, the replacement block detection circuit 802 reads the block designation address (011). It is detected that the and the alternative information (0111) stored and held in the alternative register 801 match, and a high level is derived and given to N0R85. In response, NOR gate 85 inhibits selection of decoder 28 and enables selection of decoder 86. In response, the decoder 86 determines that the alternative register address is "OO" based on the fact that a high level is not derived from either of the OR gates 85a and 85b, and corresponds to the code "00". Select an alternative memory block 30 to be used. In this way, memory block 23 becomes invalid and alternative memory block 30 is selected in its place.

In addition, when selecting other alternative memory blocks 31, 32, 33, roIJ is used as an alternative register address.
, rto'', rz'' to the decoder 84.

FIG. 5 is a specific circuit diagram of still another embodiment of the present invention. In this embodiment, one memory block included in the memory device 2 is used as an alternative memory block without providing the alternative memory device 3. That is, normally eight blocks of memory blocks 20 to 27 are memory accessed, but if a defective memory block occurs in any one of the seven blocks of memory blocks 20 to 26, memory block 27 of the highest block number is accessed.
is used as an alternative memory block in place of a defective memory block. At this time, memory access is limited to seven memory blocks 20-26. Furthermore, if the memory block 27 becomes a defective memory block,
By simply disconnecting it from the memory system without replacing it, the remaining seven memory blocks 20-2
Use 6.

Next, with reference to FIGS. 1 and 5, the specific operation of FIG. 5 will be described. If there are no bad memory blocks,
The BAD output of the alternative register 81 is logic "0" (ie, low level), and the output of the alternative block/lock detection circuit 82 is low level.

Therefore, the input of the NAND gate 871 that selects the memory block 27 is BAD=O, and the NOR gate 87
2 input (i.e., the output of inverter 83) is logic "1".
”, the memory block 27 is selected when the output Y7 of the decoder 28 is at a low level.

On the other hand, if a defective memory block occurs in any of the memory blocks 20 to 26, it becomes necessary to select memory block 27 in place of the defective memory block. At this time, a code rozB representing a defective memory block (for example, block 3) is given from the CPU I and stored in the substitute register 81. Therefore, alternative register 8
The output of the lower 1 bit of 1 becomes high level and is applied as one input to alternative block detection circuit 82 and NAND gate 871. In this state, when the CPU derives the code ro134 as a block designation address and supplies it to the decoder 28 and the alternative block detection circuit 82, the alternative block detection circuit 82 derives a high level and inhibits the output of the decoder 28. It is applied to one input of a NOR gate 872 via an inverter 83.

As a result, the memory block 27 is substituted for the defective memory block 23.

Next, considering the memory usage efficiency of the embodiment shown in FIG. 2 and this embodiment, the number of normally used memory blocks in the embodiment shown in FIG.
Therefore, u=o, s9, that is, the memory usage efficiency is 89%. On the other hand, according to the embodiment shown in FIG. 5, all eight memory blocks 20 to 27 are used in the normal state, so if there is no defective memory block, one
The usage efficiency is 0.00chi. On the other hand, memory block 20~
If any one of the 26 7 blocks becomes a defective memory, the usage efficiency will be i=0.88, or 88%. Therefore, the embodiment shown in FIG. 5 has the advantage of very high usage efficiency compared to the embodiment shown in FIG. 2, assuming that replacement frequency is low. However, when the need for replacement arises, there is a constraint that the memory space is reduced from 128 bytes to 112 bytes.

FIG. 6 is a specific electrical circuit diagram of still another embodiment of the present invention. This embodiment is a modification of the embodiment shown in FIG. 5, in which an upper block among a plurality of memory blocks 20 to 27 included in the basic memory device 2 can be used as an alternative memory block for a lower block. It is. The operation of this embodiment is basically the same as that of the embodiment shown in FIG. Therefore, common parts in terms of circuit configuration are indicated by the same reference numerals, and detailed explanations of their operations will be omitted.

<Effects> As described above, according to the present invention, alternative information consisting of a bit pattern indicating that there is a defective memory block is
A predetermined fuse can be visually recognized by a group of blown fuses according to the bit pattern of the replacement information, and therefore, when replacing a defective memory block, the defective memory block can be easily recognized, and the replacement work of the defective memory block during maintenance etc. can be done quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the principle of the invention. Second
The figure is a specific circuit diagram of an embodiment of the present invention. Third
The figure is a specific circuit diagram of the alternative memory circuit. FIG. 4, FIG. 5, and FIG. 6 are specific circuit diagrams of other embodiments of the present invention. In the figure, I is a central processing unit (CPU), 2 is a basic memory device, 20 to 27 are memory blocks, 28 is a block selection decoder, 3 is an alternative memory device, 30 to 38 are alternative memory blocks, and 4 is an address bus. , 5 is a bidirectional data bus, 6 is a control data line, 7 is a clock signal line, 8 is a switching control means which is a feature of the present invention, 81
,801゜811.821,831 are alternative registers, 8
1' is an alternative storage circuit, 82, 802, 812, 822゜832Ifi alternative block detection circuit, 83 is an innoctor, 84 and 86 are decoders, 85, 85 a +
871-878 are gates, H2-H4 are fuses, DR
I-DR4 indicates a driver. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Procedural amendment (method) July 28, 1985 1. Case indication Patent application 1986-62037 2. Name of the invention Memory block switching control device 3. Amendment Relationship with the case of a person who does

Claims (1)

[Scope of Claims] 1. A memory device including a plurality of memory blocks, and a replacement memory device having a storage capacity corresponding to at least one memory block included in the memory device, wherein a defective memory block of the memory device is provided. A device for detecting a defective memory block and switching the detected defective memory block to the alternative memory device, wherein the alternative information is provided to store and hold alternative information consisting of a bit pattern indicating that there is a defective memory block. has a number of fuses corresponding to the number of bits of the substitute information, and a blowout circuit that blows out a predetermined fuse according to the bit pattern of the alternative information, and a defective memory block is indicated based on the blowout state of the fuse. A memory block switching control device characterized by: