JPS5621349A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS5621349A
JPS5621349A JP9710479A JP9710479A JPS5621349A JP S5621349 A JPS5621349 A JP S5621349A JP 9710479 A JP9710479 A JP 9710479A JP 9710479 A JP9710479 A JP 9710479A JP S5621349 A JPS5621349 A JP S5621349A
Authority
JP
Japan
Prior art keywords
cover
seal
solder
supporting base
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9710479A
Other languages
Japanese (ja)
Inventor
Takashi Haraguchi
Takehisa Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9710479A priority Critical patent/JPS5621349A/en
Publication of JPS5621349A publication Critical patent/JPS5621349A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the droop of solder at the time of seal and sticking and to facilitate the positioning with a supporting base by adhering a metallic plate at a region except the seal and sticking section of a soldering layer provided at the whole surface of the inside of a metallic cover. CONSTITUTION:A metallic cover 13 is sealed with solder 14 through metallic layers 12 at the circumference edge section of a ceramic supporting base 1. The cover 13 is coated and sticked with a soldering layer 14 for seal and an Ni plated Koval plate 15 is previously welded to the part except the seal and sticking region. The cover 13 is placed on the supporting base 1 for heating and the solder 14 is melted to seal and stick the cover 13. In this case, the solder will not droop in the inside of a package due to the arrangement of the Koval plate 15. The positioning of the cover and the supporting base also becomes easy and alpha-ray irradiation from the soldering layer 14 is also shielded by the Koval plate 15 to prevent the deterioration in characteristics. Therefore, the efficiency of work is improved and reliability also increases.
JP9710479A 1979-07-30 1979-07-30 Package for integrated circuit Pending JPS5621349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9710479A JPS5621349A (en) 1979-07-30 1979-07-30 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9710479A JPS5621349A (en) 1979-07-30 1979-07-30 Package for integrated circuit

Publications (1)

Publication Number Publication Date
JPS5621349A true JPS5621349A (en) 1981-02-27

Family

ID=14183292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9710479A Pending JPS5621349A (en) 1979-07-30 1979-07-30 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS5621349A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539622A (en) * 1981-06-25 1985-09-03 Fujitsu Limited Hybrid integrated circuit device
US4570708A (en) * 1982-04-30 1986-02-18 Skf Steel Engineering Ab Method of using pipes resistant to hydrosulphuric acid
US5262751A (en) * 1991-12-12 1993-11-16 Yazaki Corporation Fuse

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539622A (en) * 1981-06-25 1985-09-03 Fujitsu Limited Hybrid integrated circuit device
US4570708A (en) * 1982-04-30 1986-02-18 Skf Steel Engineering Ab Method of using pipes resistant to hydrosulphuric acid
US5262751A (en) * 1991-12-12 1993-11-16 Yazaki Corporation Fuse

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