JPS5617446A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPS5617446A
JPS5617446A JP9162879A JP9162879A JPS5617446A JP S5617446 A JPS5617446 A JP S5617446A JP 9162879 A JP9162879 A JP 9162879A JP 9162879 A JP9162879 A JP 9162879A JP S5617446 A JPS5617446 A JP S5617446A
Authority
JP
Japan
Prior art keywords
address
test
contents
circuit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9162879A
Other languages
Japanese (ja)
Other versions
JPS6010665B2 (en
Inventor
Jiro Kobayashi
Koji Tanagawa
Kimito Horie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP54091628A priority Critical patent/JPS6010665B2/en
Publication of JPS5617446A publication Critical patent/JPS5617446A/en
Publication of JPS6010665B2 publication Critical patent/JPS6010665B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To prvent software from being copied and then to make a test by reading a program of a microcomputer by applying a test pulse to a test-function common terminal.
CONSTITUTION: The contents of program counter (PC)4 are cleared and the contents of address 0 of internal ROM3 are transferred to instruction register (IR)5. With a pulse applied to test-function common terminal 9, AND circuit 8 opens to reset IR5 and the contents of ROM3 are written in output port 2 and then output. Through the same operation repeated as mentioned above, AND circuit 7 detects the contents of PC4 reaching address N to set flip-flop 6 and AND circuit 8 is closed to inhibit a test pulse. Therefore, PC4 indicates address M with the instruction of address N, i.e. a jump instruction to address M.
COPYRIGHT: (C)1981,JPO&Japio
JP54091628A 1979-07-20 1979-07-20 microcomputer Expired JPS6010665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54091628A JPS6010665B2 (en) 1979-07-20 1979-07-20 microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54091628A JPS6010665B2 (en) 1979-07-20 1979-07-20 microcomputer

Publications (2)

Publication Number Publication Date
JPS5617446A true JPS5617446A (en) 1981-02-19
JPS6010665B2 JPS6010665B2 (en) 1985-03-19

Family

ID=14031810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54091628A Expired JPS6010665B2 (en) 1979-07-20 1979-07-20 microcomputer

Country Status (1)

Country Link
JP (1) JPS6010665B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59146350A (en) * 1983-02-09 1984-08-22 Nec Corp Microcomputer
JPS59231654A (en) * 1983-06-15 1984-12-26 Hitachi Ltd Semiconductor integrated circuit device and its inspecting method
JPH05505695A (en) * 1991-03-07 1993-08-19 デジタル　イクイプメント　コーポレーション An improved software debugging system and method specifically for debugging code within a multi-architecture environment.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59146350A (en) * 1983-02-09 1984-08-22 Nec Corp Microcomputer
JPS59231654A (en) * 1983-06-15 1984-12-26 Hitachi Ltd Semiconductor integrated circuit device and its inspecting method
JPH0554139B2 (en) * 1983-06-15 1993-08-11 Hitachi Ltd
JPH05505695A (en) * 1991-03-07 1993-08-19 デジタル　イクイプメント　コーポレーション An improved software debugging system and method specifically for debugging code within a multi-architecture environment.

Also Published As

Publication number Publication date
JPS6010665B2 (en) 1985-03-19

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