JPS561678A - Reading circuit for several information - Google Patents
Reading circuit for several informationInfo
- Publication number
- JPS561678A JPS561678A JP7776579A JP7776579A JPS561678A JP S561678 A JPS561678 A JP S561678A JP 7776579 A JP7776579 A JP 7776579A JP 7776579 A JP7776579 A JP 7776579A JP S561678 A JPS561678 A JP S561678A
- Authority
- JP
- Japan
- Prior art keywords
- region
- memory
- color code
- address signal
- read out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
- G09G1/02—Storage circuits
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Television Signal Processing For Recording (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To ensure an effective use of the memory by dividing the refresh memory groups into the pattern storing region and the color code region and then giving the switching to the address signal which reads the other data while the information of one region is read out to carry out the serial conversion. CONSTITUTION:Main memory 20 is formed with refresh memories M1-M8, and the memory region is devided into the pattern storing region of the fixed bit and the color code memory region each. The parallel bit outputs of memories M1-M8 are read out in the access time of fc/8-fc/4, supplied to parallel-serial converting circuit PSC to be converted into the patterns and the characters each, and then applied to signal process circuit 16 in the form of load pulse LP. While the serial conversion is given to these patterns and characters, the switching is given to the address signal in order to read out the data of the color code memory region and via address signal generating circuit ADG, latch circuit LTH plus gate circuits Gr, Gg, Gb, etc. As a result, memory 20 can be read in a high efficiency.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7776579A JPS561678A (en) | 1979-06-19 | 1979-06-19 | Reading circuit for several information |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7776579A JPS561678A (en) | 1979-06-19 | 1979-06-19 | Reading circuit for several information |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS561678A true JPS561678A (en) | 1981-01-09 |
JPH0374078B2 JPH0374078B2 (en) | 1991-11-25 |
Family
ID=13643026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7776579A Granted JPS561678A (en) | 1979-06-19 | 1979-06-19 | Reading circuit for several information |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS561678A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5462728A (en) * | 1977-10-27 | 1979-05-21 | Matsushita Electric Ind Co Ltd | Raster scan display unit |
-
1979
- 1979-06-19 JP JP7776579A patent/JPS561678A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5462728A (en) * | 1977-10-27 | 1979-05-21 | Matsushita Electric Ind Co Ltd | Raster scan display unit |
Also Published As
Publication number | Publication date |
---|---|
JPH0374078B2 (en) | 1991-11-25 |
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