JPS56167356A - Manufacture of tape carrier substrate - Google Patents

Manufacture of tape carrier substrate

Info

Publication number
JPS56167356A
JPS56167356A JP7120280A JP7120280A JPS56167356A JP S56167356 A JPS56167356 A JP S56167356A JP 7120280 A JP7120280 A JP 7120280A JP 7120280 A JP7120280 A JP 7120280A JP S56167356 A JPS56167356 A JP S56167356A
Authority
JP
Japan
Prior art keywords
layer
resist
etching
carrier substrate
fused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7120280A
Other languages
Japanese (ja)
Inventor
Masao Hayakawa
Takamichi Maeda
Masao Kumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP7120280A priority Critical patent/JPS56167356A/en
Publication of JPS56167356A publication Critical patent/JPS56167356A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the break at shoulder part of the conductive metal foil as well as to improve the yield rate for the subject tape carrier substrate by a method wherein the etching process for formation of an inner lead pattern is performed using the plated layer, which was fused and highly densed, as a mask. CONSTITUTION:After a device hole 3 and a through hole 10 have been formed on the polyimide tape 1 whereon a copper foils 2 and 4 were laminated on both sides, a Cu plated layer 5 is formed by performing a back filling processing using a resist 9. Then, a resist layer 6 is provided and a plating is performed on the Sn layer 7 to be used for an etching mask. Then, the resist is removed and after the Sn layer 7 has been fused and highly densed by performing a heat treatment in a silicon oil, for example, a back filling processing is performed again and a Cu layer ie etched, and an inner lead is formed. The Sn layer 7 is remained in the state as above- mentioned and a semiconductor chip 8 is eulectically connected. Through these procedures, the breaking of wire due to the step at sholder part when performing an etching can be prevented and the yield rate for the substrate can be improved.
JP7120280A 1980-05-27 1980-05-27 Manufacture of tape carrier substrate Pending JPS56167356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7120280A JPS56167356A (en) 1980-05-27 1980-05-27 Manufacture of tape carrier substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7120280A JPS56167356A (en) 1980-05-27 1980-05-27 Manufacture of tape carrier substrate

Publications (1)

Publication Number Publication Date
JPS56167356A true JPS56167356A (en) 1981-12-23

Family

ID=13453844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7120280A Pending JPS56167356A (en) 1980-05-27 1980-05-27 Manufacture of tape carrier substrate

Country Status (1)

Country Link
JP (1) JPS56167356A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114211A2 (en) * 1982-12-27 1984-08-01 International Business Machines Corporation Multi-layer flexible film module
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114211A2 (en) * 1982-12-27 1984-08-01 International Business Machines Corporation Multi-layer flexible film module
JPH02209742A (en) * 1988-09-16 1990-08-21 Natl Semiconductor Corp <Ns> Gold/tin entectic bonding for tape automaization bonding process

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