JPS56167328A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56167328A
JPS56167328A JP7037480A JP7037480A JPS56167328A JP S56167328 A JPS56167328 A JP S56167328A JP 7037480 A JP7037480 A JP 7037480A JP 7037480 A JP7037480 A JP 7037480A JP S56167328 A JPS56167328 A JP S56167328A
Authority
JP
Japan
Prior art keywords
marker
resist
rays
forming
irradiation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7037480A
Other languages
Japanese (ja)
Inventor
Makoto Yoshimi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7037480A priority Critical patent/JPS56167328A/en
Publication of JPS56167328A publication Critical patent/JPS56167328A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To prevent deformation of a marker, and therefore, piling of layers can be achieved with a high accuracy, in a circuit pattern forming process by an irradiation with electron rays, by setting amounts of rays for the irradiation to the marker and the surrounding area to a value within an inversion region of resist sensitivity characteristics. CONSTITUTION:In a selective oxidizing process of MOSIC, etc., after forming an oxide film 8 and a nitride film 9 on a substrate 7 having a convex type marker 2, by coating such a material as a positive resist PMMA10, it is exposed to electronic rays 11 and 12. At this time, amounts of exposure to the marker 2 and the surrounding area are so adjusted as to cause a negative inversion of approximately 2X10<-3>Coulomb/cm<2>. It is possible, by doing so, to remove only the resist 10 of a separating region after development, and by enabling to leave the nitride film 9 on the marker 2, it is possible to prevent variation of the marker 2 due to the formation of a selective oxidizing layer 14. Likewise, if this is applied to a process of forming such a material as a gate poly Si pattern by a negative resist, the poly Si layer can be completely removed from the marker 2, and the accuracy of the marker can be maintained.
JP7037480A 1980-05-27 1980-05-27 Manufacture of semiconductor device Pending JPS56167328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7037480A JPS56167328A (en) 1980-05-27 1980-05-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7037480A JPS56167328A (en) 1980-05-27 1980-05-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56167328A true JPS56167328A (en) 1981-12-23

Family

ID=13429595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7037480A Pending JPS56167328A (en) 1980-05-27 1980-05-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56167328A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000046845A1 (en) * 1999-02-02 2000-08-10 Nikon Corporation Method for detecting alignment mark in charged particle beam exposure apparatus
KR20030038327A (en) * 2001-11-09 2003-05-16 미쓰비시덴키 가부시키가이샤 Pattern forming method and method of fabricating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000046845A1 (en) * 1999-02-02 2000-08-10 Nikon Corporation Method for detecting alignment mark in charged particle beam exposure apparatus
KR20030038327A (en) * 2001-11-09 2003-05-16 미쓰비시덴키 가부시키가이샤 Pattern forming method and method of fabricating device

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