JPS56162127A - Process input/output device - Google Patents

Process input/output device

Info

Publication number
JPS56162127A
JPS56162127A JP6512180A JP6512180A JPS56162127A JP S56162127 A JPS56162127 A JP S56162127A JP 6512180 A JP6512180 A JP 6512180A JP 6512180 A JP6512180 A JP 6512180A JP S56162127 A JPS56162127 A JP S56162127A
Authority
JP
Japan
Prior art keywords
data
cpu1
ram
plant
process input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6512180A
Other languages
Japanese (ja)
Inventor
Toru Hagiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6512180A priority Critical patent/JPS56162127A/en
Publication of JPS56162127A publication Critical patent/JPS56162127A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13012—Using other programs, adapting program to machine, exchanging or rom
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15048—Microprocessor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15067—Using a mixture of memories

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Control By Computers (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To work out a design change of the control method for a process input/ output data with a simple operation, by using an RAM for a memory device which is used for processing a signal in a process input/output device. CONSTITUTION:An output data which is outputted for controlling a plant from a CPU1, and a data which is inputted to the CPU1 from the plant are processed through a process input/output device 2. On the device 2 are provided control cards 4a-4c, and the respective different cards are prepared depending on the kind and contents of a process data. These cards are provided with an RAM, and a data from the plant is covered by a program which has been written in the RAM, and is transferred to the CPU1, and a data from the CPU1 is also converted by this program, and is sent as a control data to the plant from the device 2. Since an RAM is used for a card 4, a correction can be made easily even after the system has started up its operation, and also since a data is stored in the RAM without passing through a main memory device of the CPU1, the processing is executed at a high speed.
JP6512180A 1980-05-16 1980-05-16 Process input/output device Pending JPS56162127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6512180A JPS56162127A (en) 1980-05-16 1980-05-16 Process input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6512180A JPS56162127A (en) 1980-05-16 1980-05-16 Process input/output device

Publications (1)

Publication Number Publication Date
JPS56162127A true JPS56162127A (en) 1981-12-12

Family

ID=13277726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6512180A Pending JPS56162127A (en) 1980-05-16 1980-05-16 Process input/output device

Country Status (1)

Country Link
JP (1) JPS56162127A (en)

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