JPS56153861A - By-pass line system in dsi processing device - Google Patents

By-pass line system in dsi processing device

Info

Publication number
JPS56153861A
JPS56153861A JP5695880A JP5695880A JPS56153861A JP S56153861 A JPS56153861 A JP S56153861A JP 5695880 A JP5695880 A JP 5695880A JP 5695880 A JP5695880 A JP 5695880A JP S56153861 A JPS56153861 A JP S56153861A
Authority
JP
Japan
Prior art keywords
pass line
pass
circuits
processing device
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5695880A
Other languages
Japanese (ja)
Inventor
Kenichi Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5695880A priority Critical patent/JPS56153861A/en
Publication of JPS56153861A publication Critical patent/JPS56153861A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/17—Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • H04J3/172—Digital speech interpolation, i.e. DSI

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To relieve all circuits from disconnection easily, by avoiding disconnection of all connected circuits at the fault occurrence time, in the digital speech interpolation device. CONSTITUTION:When a fault occurs in processing parts such as voice detector 11, assigning processor 12, and circuit assigning register 13 in the transmission paet, multiplexer 39 is switched to by-pass line part 51. Further, fault information is transferred to the receiving side, and multiplexer 40 is switched to by-pass line part 52. As a result, by-pass lines are formed in the transmission part as well as the receiving part, and the whole of lines is not disconnected and is relieved by by-pass circuits at the normalcy time.
JP5695880A 1980-04-28 1980-04-28 By-pass line system in dsi processing device Pending JPS56153861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5695880A JPS56153861A (en) 1980-04-28 1980-04-28 By-pass line system in dsi processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5695880A JPS56153861A (en) 1980-04-28 1980-04-28 By-pass line system in dsi processing device

Publications (1)

Publication Number Publication Date
JPS56153861A true JPS56153861A (en) 1981-11-28

Family

ID=13042041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5695880A Pending JPS56153861A (en) 1980-04-28 1980-04-28 By-pass line system in dsi processing device

Country Status (1)

Country Link
JP (1) JPS56153861A (en)

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