JPS56115050A - Input buffer circuit - Google Patents

Input buffer circuit

Info

Publication number
JPS56115050A
JPS56115050A JP1887180A JP1887180A JPS56115050A JP S56115050 A JPS56115050 A JP S56115050A JP 1887180 A JP1887180 A JP 1887180A JP 1887180 A JP1887180 A JP 1887180A JP S56115050 A JPS56115050 A JP S56115050A
Authority
JP
Japan
Prior art keywords
terminal
input buffer
occurrence
same time
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1887180A
Other languages
Japanese (ja)
Inventor
Takehiko Umeyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1887180A priority Critical patent/JPS56115050A/en
Publication of JPS56115050A publication Critical patent/JPS56115050A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE: To prevent both the occurrence of signal distortion and the noise overlap, by dividing the input buffer into plural systems in a stereo demodulator circuit and at the same time using a combination of the NPN and PNP transistors.
CONSTITUTION: The input signal supplied through the terminal 3 is delivered to the terminal 5 via the NPN transistor TR20 and PNPTR21 as well as to the terminal 4 via TR20 and PNPTR22 each. As a result, the occurrence of signal distortion due to the next-stage circuit to be connected to the terminal 5 can be prevented. At the same time, the noise of the next-stage circuit is never inducted to the terminal 4. Furthermore the strain caused by the single TR can be reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP1887180A 1980-02-18 1980-02-18 Input buffer circuit Pending JPS56115050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1887180A JPS56115050A (en) 1980-02-18 1980-02-18 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1887180A JPS56115050A (en) 1980-02-18 1980-02-18 Input buffer circuit

Publications (1)

Publication Number Publication Date
JPS56115050A true JPS56115050A (en) 1981-09-10

Family

ID=11983596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1887180A Pending JPS56115050A (en) 1980-02-18 1980-02-18 Input buffer circuit

Country Status (1)

Country Link
JP (1) JPS56115050A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794816A (en) * 1985-10-15 1989-01-03 Tokai Rubber Industries, Ltd. Dual-type damper device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794816A (en) * 1985-10-15 1989-01-03 Tokai Rubber Industries, Ltd. Dual-type damper device
US4881426A (en) * 1985-10-15 1989-11-21 Tokai Rubber Industries, Ltd. Dual-type damper device

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