JPS56152323A - Digital phase detecting circuit - Google Patents
Digital phase detecting circuitInfo
- Publication number
- JPS56152323A JPS56152323A JP5665180A JP5665180A JPS56152323A JP S56152323 A JPS56152323 A JP S56152323A JP 5665180 A JP5665180 A JP 5665180A JP 5665180 A JP5665180 A JP 5665180A JP S56152323 A JPS56152323 A JP S56152323A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- pulse
- reference clock
- signal
- reference value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To improve the comparison precision, by latching the frequency division output of reference clock pulses by the single pulse of clock pulses, which are synchronized with reference clock pulses, to be measured and by comparing it with the reference value. CONSTITUTION:The reference clock pulse signal inputted from input terminal 3 is frequency-divided by n-bit binary counter 70. The clock pulse signal, which is inputted from input terminal 2, to be measured is applied to signal pulse generating circuit 14 and becomes single pulse 1d synchronized with the reference clock pulse. By this single pulse 1d, n-bit parallel output 7a of n-bit binary counter 70 is latched in n-bit latch memory 80. Output 8a of n-bit latch memory 80 and plural n-bit reference value outputs 10a of n-bit reference value generating circuit 100 are compared with each other by n-bit magnitude comparator 90, and advance or delay decision signal 4a or 4b is outputted in accordance with the comparison result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5665180A JPS56152323A (en) | 1980-04-25 | 1980-04-25 | Digital phase detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5665180A JPS56152323A (en) | 1980-04-25 | 1980-04-25 | Digital phase detecting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56152323A true JPS56152323A (en) | 1981-11-25 |
Family
ID=13033260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5665180A Pending JPS56152323A (en) | 1980-04-25 | 1980-04-25 | Digital phase detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56152323A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230214A (en) * | 1988-07-20 | 1990-01-31 | Nec Corp | Phase comparing circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131765A (en) * | 1973-04-24 | 1974-12-17 |
-
1980
- 1980-04-25 JP JP5665180A patent/JPS56152323A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131765A (en) * | 1973-04-24 | 1974-12-17 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230214A (en) * | 1988-07-20 | 1990-01-31 | Nec Corp | Phase comparing circuit |
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