JPS56143589A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS56143589A
JPS56143589A JP4624880A JP4624880A JPS56143589A JP S56143589 A JPS56143589 A JP S56143589A JP 4624880 A JP4624880 A JP 4624880A JP 4624880 A JP4624880 A JP 4624880A JP S56143589 A JPS56143589 A JP S56143589A
Authority
JP
Japan
Prior art keywords
turned
held
power source
memory device
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4624880A
Other languages
Japanese (ja)
Inventor
Yutaka Kumagai
Yukio Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4624880A priority Critical patent/JPS56143589A/en
Publication of JPS56143589A publication Critical patent/JPS56143589A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To minimize power consumption in the backup operation of a CMOS memory device by detecting a drop in power source voltage and by controlling so that a power source current will be minimized in response to the detection output. CONSTITUTION:When the memory device is held in information holding mode, namely, when power source voltage V1 is held at the low voltage level, transistor (TR) Q17 is cut off and the potential at coupling point P3 is held at the high level. Then, TRQ15 is turned off and TRQ16 is turned on, so that a control voltage which is the output of the inverter of Q15 and Q16 will be held at the low level. At this time, TRQ13 of input circuit 1 is turned on and TRQ14 is turned off to hold output point P2 at the high level. Since TRQ14 is cut off, power source current I never flows through input circuit 1 and the power consumption is zero.
JP4624880A 1980-04-10 1980-04-10 Semiconductor memory device Pending JPS56143589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4624880A JPS56143589A (en) 1980-04-10 1980-04-10 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4624880A JPS56143589A (en) 1980-04-10 1980-04-10 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS56143589A true JPS56143589A (en) 1981-11-09

Family

ID=12741846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4624880A Pending JPS56143589A (en) 1980-04-10 1980-04-10 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS56143589A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147190A (en) * 1981-03-05 1982-09-10 Nec Corp Memory circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147190A (en) * 1981-03-05 1982-09-10 Nec Corp Memory circuit
JPS6160513B2 (en) * 1981-03-05 1986-12-20 Nippon Electric Co

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