JPS56160060A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS56160060A JPS56160060A JP6306180A JP6306180A JPS56160060A JP S56160060 A JPS56160060 A JP S56160060A JP 6306180 A JP6306180 A JP 6306180A JP 6306180 A JP6306180 A JP 6306180A JP S56160060 A JPS56160060 A JP S56160060A
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- type mos
- bias
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE: To constitute the circuit having small power consumption by a method wherein an E-type MOS transistor and an I-type MOS transistor are connected through the intermediary of the load resistor and a self-bias voltage is applied to these transistors.
CONSTITUTION: The E-type MOS transistor T4 and the I-type MOS transistor T5 are connected through the load resistor R1 as shown in the diagram. On the substrates of the transistors T4 and T5, a back bias VB is applied from terminals 3-4 and 3-5. The back bias VB is controlled in such manner that about -2.5V, CE' is maintained when a chip enable signal CE' is HIGH and about -6V when it is LOW. This function can be performed automatically using the self-bias generating device as shown in the diagram. Through these procedures, VB becomes approximately -6V when the CE' is LOW and the I-type MOS transistor T5 begins to perform the function of the E-type. As a result, the current passing this point is interrupted.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6306180A JPS56160060A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
US06/260,994 US4460835A (en) | 1980-05-13 | 1981-05-06 | Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator |
DE8181103606T DE3162416D1 (en) | 1980-05-13 | 1981-05-11 | Semiconductor integrated circuit device |
EP81103606A EP0039946B1 (en) | 1980-05-13 | 1981-05-11 | Semiconductor integrated circuit device |
CA000377457A CA1185665A (en) | 1980-05-13 | 1981-05-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6306180A JPS56160060A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56160060A true JPS56160060A (en) | 1981-12-09 |
JPH0142142B2 JPH0142142B2 (en) | 1989-09-11 |
Family
ID=13218442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6306180A Granted JPS56160060A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56160060A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5768062A (en) * | 1980-10-15 | 1982-04-26 | Toshiba Corp | Semiconductor integrated circuit device |
-
1980
- 1980-05-13 JP JP6306180A patent/JPS56160060A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5768062A (en) * | 1980-10-15 | 1982-04-26 | Toshiba Corp | Semiconductor integrated circuit device |
JPH0358182B2 (en) * | 1980-10-15 | 1991-09-04 | Tokyo Shibaura Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPH0142142B2 (en) | 1989-09-11 |
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