JPS5613738A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5613738A
JPS5613738A JP8965479A JP8965479A JPS5613738A JP S5613738 A JPS5613738 A JP S5613738A JP 8965479 A JP8965479 A JP 8965479A JP 8965479 A JP8965479 A JP 8965479A JP S5613738 A JPS5613738 A JP S5613738A
Authority
JP
Japan
Prior art keywords
resin
materials
radiant plate
leads
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8965479A
Other languages
Japanese (ja)
Inventor
Takeshi Ohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP8965479A priority Critical patent/JPS5613738A/en
Publication of JPS5613738A publication Critical patent/JPS5613738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To decrease the quantity of waste resin without damaging a burr formation preventive effect by a method wherein resin materials are erected at the fringe of a radiant plate of a semiconductor device when sealing the plate with resin, and the materials are removed after sealing. CONSTITUTION:Leads 31, 37 are caulked 2 to a radiant plate 1, and leads 32-36 are soldered onto the radiant plate, and connected 5 to an electrode of a semiconductor element 4. The fringe of the back 1b of the radiant plate 1 is oppositely arranged to a groove 8 of an upper metal mold 6, an end surface of the radiant plate and an outside wall of the groove 8 are conformed, and the leads 3 are held by a cope 6 and a drag 9. A resin material 11' is filled into a cavity and also injected into the groove 8 forcedly. When removing a sealing body from the molds, resin materials 12 are erected. When the materials 12 are pushed in the arrow head direction, they can simply be removed, a device which burr is not formed can be obtained, and external appearance is excellent. Since the quantity of the resin materials 12 is extremely small, the quantity of resin discarded is sharply decreased.
JP8965479A 1979-07-13 1979-07-13 Manufacture of semiconductor device Pending JPS5613738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8965479A JPS5613738A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8965479A JPS5613738A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5613738A true JPS5613738A (en) 1981-02-10

Family

ID=13976739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8965479A Pending JPS5613738A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5613738A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065555A (en) * 1983-09-20 1985-04-15 Toshiba Corp Manufacture of resin-seal semiconductor device
JPS63211638A (en) * 1988-01-08 1988-09-02 Nec Home Electronics Ltd Manufacture of resin seal type semiconductor device
US5670429A (en) * 1993-06-30 1997-09-23 Rohm Co. Ltd. Process of conveying an encapsulated electronic component by engaging an integral resin projection

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123874A (en) * 1976-04-09 1977-10-18 Mitsubishi Electric Corp Producing device for plastic molded type semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123874A (en) * 1976-04-09 1977-10-18 Mitsubishi Electric Corp Producing device for plastic molded type semiconductor devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065555A (en) * 1983-09-20 1985-04-15 Toshiba Corp Manufacture of resin-seal semiconductor device
JPH0444416B2 (en) * 1983-09-20 1992-07-21 Tokyo Shibaura Electric Co
JPS63211638A (en) * 1988-01-08 1988-09-02 Nec Home Electronics Ltd Manufacture of resin seal type semiconductor device
US5670429A (en) * 1993-06-30 1997-09-23 Rohm Co. Ltd. Process of conveying an encapsulated electronic component by engaging an integral resin projection
US5739054A (en) * 1993-06-30 1998-04-14 Rohm Co., Ltd. Process for forming an encapsulated electronic component having an integral resin projection
US5760481A (en) * 1993-06-30 1998-06-02 Rohm Co., Ltd. Encapsulated electronic component containing a holding member

Similar Documents

Publication Publication Date Title
ES448865A1 (en) Method of and apparatus for molding a receptacle
JPS5613738A (en) Manufacture of semiconductor device
JPS553972A (en) Method of and mold for injection molding of patterned mold
JPS5476658A (en) Molding of synthetic resin article
JPS5664458A (en) Metallic body
JPS5569421A (en) Modling of frame for electric appliance
JPS54162963A (en) Manufacture of resin-sealed semiconductor device
JPS55100140A (en) Molding method and molding
JPS5460565A (en) Parts molding method
JPS5672431A (en) Manufacture of reflective type screen
JPS562642A (en) Device for forming resin-sealed semiconductor device
JPS546169A (en) Production of insulative pannel
JPS5510860A (en) Method of manufacturing coreless motor
JPS641513A (en) Molding of thick-wall product
JPS5487760A (en) Method of injection molding of synthetic resin
JPS5766818A (en) Method of shaping dies
JPS55159932A (en) Preparation of wooden top board
JPS5720437A (en) Resin sealing metal mold for semiconductor device
JPS5263301A (en) Housing and its preparation
JPS57168207A (en) Manufacture of optical fiber device
JPS5622642A (en) Manufacture of hollow transparent object
JPS57105306A (en) Method of moldng synthetic resin article
JPS5724233A (en) Integral molding method for tabular body
JPS5687330A (en) Manufacture of semiconductor device
JPS5753339A (en) Manufacture of tire mold