JPS5613586A - Semiconductor memory circuit - Google Patents
Semiconductor memory circuitInfo
- Publication number
- JPS5613586A JPS5613586A JP8889779A JP8889779A JPS5613586A JP S5613586 A JPS5613586 A JP S5613586A JP 8889779 A JP8889779 A JP 8889779A JP 8889779 A JP8889779 A JP 8889779A JP S5613586 A JPS5613586 A JP S5613586A
- Authority
- JP
- Japan
- Prior art keywords
- array
- memory circuit
- output terminal
- circuit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To make it possible to obtain a circuit of high flexibility and availability by constituting on the same circuit an address decoder, memory circuit, data-selecting decoder, AND array, and OR array. CONSTITUTION:Four row-read bits of memory circuit 300, selected on the basis of a combination of signal values of input terminals 1 and 2, are transferred to AND array 600 of program logic array 400 by way of output terminals 305-308. In array 600, read data selecting decoder 500, for example, when a selective signal supplied to input terminal 602 is significant, selects and sends data of input terminal 610 to output terminal 606. Then, OR array 700 sends a selected one-bit signals, supplied to one of input terminals 701-704, to output terminal 5 by way of output terminal 705.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8889779A JPS5613586A (en) | 1979-07-13 | 1979-07-13 | Semiconductor memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8889779A JPS5613586A (en) | 1979-07-13 | 1979-07-13 | Semiconductor memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5613586A true JPS5613586A (en) | 1981-02-09 |
Family
ID=13955744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8889779A Pending JPS5613586A (en) | 1979-07-13 | 1979-07-13 | Semiconductor memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5613586A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58105477A (en) * | 1981-12-16 | 1983-06-23 | Toshiba Corp | Ram control circuit |
JPH04175106A (en) * | 1990-09-27 | 1992-06-23 | Takemasa Iijima | Using method for waste stone material |
-
1979
- 1979-07-13 JP JP8889779A patent/JPS5613586A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58105477A (en) * | 1981-12-16 | 1983-06-23 | Toshiba Corp | Ram control circuit |
JPH0227759B2 (en) * | 1981-12-16 | 1990-06-19 | Tokyo Shibaura Electric Co | |
JPH04175106A (en) * | 1990-09-27 | 1992-06-23 | Takemasa Iijima | Using method for waste stone material |
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