JPS56133861A - Film carrier - Google Patents

Film carrier

Info

Publication number
JPS56133861A
JPS56133861A JP3610280A JP3610280A JPS56133861A JP S56133861 A JPS56133861 A JP S56133861A JP 3610280 A JP3610280 A JP 3610280A JP 3610280 A JP3610280 A JP 3610280A JP S56133861 A JPS56133861 A JP S56133861A
Authority
JP
Japan
Prior art keywords
window
lead frame
film carrier
semiconductor element
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3610280A
Other languages
Japanese (ja)
Inventor
Hiromi Kanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3610280A priority Critical patent/JPS56133861A/en
Publication of JPS56133861A publication Critical patent/JPS56133861A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To permit connection of high reliability by bridging one end of each lead frame over to the opposed end of the window in a film carrier as well as bending the bridge portion. CONSTITUTION:Over a window 3 provided in a tape 1, a plurality of lead frames 4 are bridged between the opposed ends, and at said window 3, each lead frame 4 has a bent portion 4b transformed upward or downward, which is connected with a bump of a semiconductor element by soldering. Thereby, the bent portion of each lead frame is hardly affected by external forces as well as can be connected with the semiconductor element bump, with said arrangement maintained at a certain degree of accuracy. Accordingly, the reliability improves.
JP3610280A 1980-03-24 1980-03-24 Film carrier Pending JPS56133861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3610280A JPS56133861A (en) 1980-03-24 1980-03-24 Film carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3610280A JPS56133861A (en) 1980-03-24 1980-03-24 Film carrier

Publications (1)

Publication Number Publication Date
JPS56133861A true JPS56133861A (en) 1981-10-20

Family

ID=12460397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3610280A Pending JPS56133861A (en) 1980-03-24 1980-03-24 Film carrier

Country Status (1)

Country Link
JP (1) JPS56133861A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139976A (en) * 1977-05-13 1978-12-06 Seiko Epson Corp Packaging method of semiconductor chips

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139976A (en) * 1977-05-13 1978-12-06 Seiko Epson Corp Packaging method of semiconductor chips

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