JPS56129430A - High-speed binary sequence circuit having feedback circuit - Google Patents

High-speed binary sequence circuit having feedback circuit

Info

Publication number
JPS56129430A
JPS56129430A JP3267080A JP3267080A JPS56129430A JP S56129430 A JPS56129430 A JP S56129430A JP 3267080 A JP3267080 A JP 3267080A JP 3267080 A JP3267080 A JP 3267080A JP S56129430 A JPS56129430 A JP S56129430A
Authority
JP
Japan
Prior art keywords
circuit
feedback
delay
binary sequence
neglected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3267080A
Other languages
Japanese (ja)
Other versions
JPH0377690B2 (en
Inventor
Yoshifumi Toda
Toshiyuki Morita
Hideaki Ito
Kiyoaki Hodohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3267080A priority Critical patent/JPS56129430A/en
Publication of JPS56129430A publication Critical patent/JPS56129430A/en
Publication of JPH0377690B2 publication Critical patent/JPH0377690B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters

Abstract

PURPOSE:To remove the limit of the maximum operating frequency of the circuit, by picking up the feedback signal from before n bits so that the delay time of the feedback can be neglected and making feedback with a delay, in a binary sequence circuit in which a plurality of FF circuits are in cascade connection. CONSTITUTION:FF circuits FF11-F13 are in cascade connection, the feedback signal is picked up from the output of FF11 and FF12 and it is fed to the delay line DL1 from the OR gate circuit G12, and delay is given by Td1 corresponding to one- bit's share and feedback input is made to the 1st stage FF11 of FF circuit. In comparison with the case that both the outputs of FF2, FF3 in FF circuit are fed directly back to FF1 conventionally, the delay time at the feedback circuit can be neglected by the feedback point before one bit, and high-speed operation can be made up to the toggle frequency of FF circuit.
JP3267080A 1980-03-17 1980-03-17 High-speed binary sequence circuit having feedback circuit Granted JPS56129430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3267080A JPS56129430A (en) 1980-03-17 1980-03-17 High-speed binary sequence circuit having feedback circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3267080A JPS56129430A (en) 1980-03-17 1980-03-17 High-speed binary sequence circuit having feedback circuit

Publications (2)

Publication Number Publication Date
JPS56129430A true JPS56129430A (en) 1981-10-09
JPH0377690B2 JPH0377690B2 (en) 1991-12-11

Family

ID=12365303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3267080A Granted JPS56129430A (en) 1980-03-17 1980-03-17 High-speed binary sequence circuit having feedback circuit

Country Status (1)

Country Link
JP (1) JPS56129430A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384493A (en) * 1991-10-03 1995-01-24 Nec Corporation Hi-speed and low-power flip-flop

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5560340A (en) * 1978-10-30 1980-05-07 Fujitsu Ltd Dividing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5560340A (en) * 1978-10-30 1980-05-07 Fujitsu Ltd Dividing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384493A (en) * 1991-10-03 1995-01-24 Nec Corporation Hi-speed and low-power flip-flop

Also Published As

Publication number Publication date
JPH0377690B2 (en) 1991-12-11

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