JPS56129419A - Delay circuit for analog signal - Google Patents

Delay circuit for analog signal

Info

Publication number
JPS56129419A
JPS56129419A JP3272880A JP3272880A JPS56129419A JP S56129419 A JPS56129419 A JP S56129419A JP 3272880 A JP3272880 A JP 3272880A JP 3272880 A JP3272880 A JP 3272880A JP S56129419 A JPS56129419 A JP S56129419A
Authority
JP
Japan
Prior art keywords
delay circuit
pulse
analog signal
switched
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3272880A
Other languages
Japanese (ja)
Inventor
Toshiro Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3272880A priority Critical patent/JPS56129419A/en
Publication of JPS56129419A publication Critical patent/JPS56129419A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H03H19/004—Switched capacitor networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To form a new analog signal delay circuit which can be used in place for a delay circuit using charge transfer elements, by the application of a switched capacitor. CONSTITUTION:A plurality of memory cells M1-Mn in parallel connection between the input terminal IN and the output terminal OUT, are formed with the switched capacitor type analog memory having the input switch SW, output switch SR, and capacitor CS. The switches SW, SR for each memory cell are circulatingly switched with the control pulses WP, RP outputted from the pulse generating circuit 20. The pulse generating circuit 20 can be formed with the shift register which sequentially shifts the clock pulse CP inputted with a prescribed period externally with the clock phi, and WP1-WPn as the input switch control pulse WP and RP1- RPn as the output switch control pulse RP are produced.
JP3272880A 1980-03-17 1980-03-17 Delay circuit for analog signal Pending JPS56129419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3272880A JPS56129419A (en) 1980-03-17 1980-03-17 Delay circuit for analog signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3272880A JPS56129419A (en) 1980-03-17 1980-03-17 Delay circuit for analog signal

Publications (1)

Publication Number Publication Date
JPS56129419A true JPS56129419A (en) 1981-10-09

Family

ID=12366896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3272880A Pending JPS56129419A (en) 1980-03-17 1980-03-17 Delay circuit for analog signal

Country Status (1)

Country Link
JP (1) JPS56129419A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184405A (en) * 1988-01-18 1989-07-24 Kumamoto Techno Porisu Zaidan Object measuring instrument
EP0607630A1 (en) * 1992-12-15 1994-07-27 Philips Patentverwaltung GmbH Circuit for delaying a useful signal
US6061279A (en) * 1998-03-11 2000-05-09 Yamaha Corporation Delay circuit for analog signals
EP1085522A1 (en) * 1999-09-15 2001-03-21 Omnivision Technologies Inc. Analog delay line for image processing
JP2007036872A (en) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd Analog memory circuit and video signal processing apparatus
US7760250B2 (en) * 2007-06-20 2010-07-20 Altasens, Inc. Method and apparatus for minimizing noise pickup in image sensors
WO2014155635A1 (en) * 2013-03-28 2014-10-02 株式会社日立製作所 Delay circuit, electronic circuit using delay circuit and ultrasonic imaging device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287341A (en) * 1976-01-16 1977-07-21 Hitachi Ltd Delay circuit for analog signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287341A (en) * 1976-01-16 1977-07-21 Hitachi Ltd Delay circuit for analog signal

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184405A (en) * 1988-01-18 1989-07-24 Kumamoto Techno Porisu Zaidan Object measuring instrument
EP0607630A1 (en) * 1992-12-15 1994-07-27 Philips Patentverwaltung GmbH Circuit for delaying a useful signal
US6061279A (en) * 1998-03-11 2000-05-09 Yamaha Corporation Delay circuit for analog signals
EP1085522A1 (en) * 1999-09-15 2001-03-21 Omnivision Technologies Inc. Analog delay line for image processing
JP2007036872A (en) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd Analog memory circuit and video signal processing apparatus
US7760250B2 (en) * 2007-06-20 2010-07-20 Altasens, Inc. Method and apparatus for minimizing noise pickup in image sensors
WO2014155635A1 (en) * 2013-03-28 2014-10-02 株式会社日立製作所 Delay circuit, electronic circuit using delay circuit and ultrasonic imaging device
JP6043867B2 (en) * 2013-03-28 2016-12-14 株式会社日立製作所 Ultrasonic imaging device
EP2980803A4 (en) * 2013-03-28 2017-03-01 Hitachi, Ltd. Delay circuit, electronic circuit using delay circuit and ultrasonic imaging device
US10389340B2 (en) 2013-03-28 2019-08-20 Hitachi, Ltd. Delay circuit, electronic circuit using delay circuit and ultrasonic imaging device

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