JPS54154241A - Signal converting circuit - Google Patents

Signal converting circuit

Info

Publication number
JPS54154241A
JPS54154241A JP6235278A JP6235278A JPS54154241A JP S54154241 A JPS54154241 A JP S54154241A JP 6235278 A JP6235278 A JP 6235278A JP 6235278 A JP6235278 A JP 6235278A JP S54154241 A JPS54154241 A JP S54154241A
Authority
JP
Japan
Prior art keywords
fet
signal
input terminal
signal row
plural units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6235278A
Other languages
Japanese (ja)
Inventor
Masayuki Katakura
Masaru Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6235278A priority Critical patent/JPS54154241A/en
Publication of JPS54154241A publication Critical patent/JPS54154241A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To eliminate the interference of the signal row which is given the timedivision multiplication through the simple circuit constitution in order to obtain the continuous signals by providing the shift register consisting of the inverter or FF which delivers the switching control signals of each switching element in synchronization with the signal row.
CONSTITUTION: Analog switch 32 is formed by connecting in parallel plural units of FET's which are connected to input terminal 31 supplying the signal row underwent the time-division multiplication. Then shift register 33 consisting of plural units of FF or the inverter is provided to the transfer gate of the FET. The timing pulse synchronized with the repetition of the time-division multiplication is applied to input terminal 34 of register 33; the clock pulse synchronized with the weighting coefficient signal row is supplied from input terminal 35; signal holding capacitor 36 is connected to the output of each FET of switch 33; and furthermore plural units of output terminals 41, 42 ... 49 are connected to form the signal converting circuit.
COPYRIGHT: (C)1979,JPO&Japio
JP6235278A 1978-05-26 1978-05-26 Signal converting circuit Pending JPS54154241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6235278A JPS54154241A (en) 1978-05-26 1978-05-26 Signal converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6235278A JPS54154241A (en) 1978-05-26 1978-05-26 Signal converting circuit

Publications (1)

Publication Number Publication Date
JPS54154241A true JPS54154241A (en) 1979-12-05

Family

ID=13197632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6235278A Pending JPS54154241A (en) 1978-05-26 1978-05-26 Signal converting circuit

Country Status (1)

Country Link
JP (1) JPS54154241A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166620A (en) * 1980-05-28 1981-12-21 Toshiba Corp Automatic equalizer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4956557A (en) * 1972-09-29 1974-06-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4956557A (en) * 1972-09-29 1974-06-01

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166620A (en) * 1980-05-28 1981-12-21 Toshiba Corp Automatic equalizer
JPS6327895B2 (en) * 1980-05-28 1988-06-06 Toshiba Kk

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