JPS5512506A - Shift register circuit - Google Patents

Shift register circuit

Info

Publication number
JPS5512506A
JPS5512506A JP8288278A JP8288278A JPS5512506A JP S5512506 A JPS5512506 A JP S5512506A JP 8288278 A JP8288278 A JP 8288278A JP 8288278 A JP8288278 A JP 8288278A JP S5512506 A JPS5512506 A JP S5512506A
Authority
JP
Japan
Prior art keywords
ram
signal
state
shift register
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8288278A
Other languages
Japanese (ja)
Inventor
Toru Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8288278A priority Critical patent/JPS5512506A/en
Publication of JPS5512506A publication Critical patent/JPS5512506A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To enable to freely set the number of shifts in matching with the respective object, by changing the state of periodical repetition of the address signal given to RAM. CONSTITUTION:The information S1 to be shifted is inputted to RAM 2, which is made alternately to write-in and readout state in a given period by the output signal S2 of the write-in/readout pulse generator 4, and the specified address for RAM 2 is repetitively designated from the address signal generator 5 in the period related to the signal S2. Further, by changing the state of repetition for the designation signal S3, the readout output of RAM 2 is delivered via FF6. As a result, the output of the shift register 1 can perform shifts in the number of addresses of RAM 2.
JP8288278A 1978-07-10 1978-07-10 Shift register circuit Pending JPS5512506A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8288278A JPS5512506A (en) 1978-07-10 1978-07-10 Shift register circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8288278A JPS5512506A (en) 1978-07-10 1978-07-10 Shift register circuit

Publications (1)

Publication Number Publication Date
JPS5512506A true JPS5512506A (en) 1980-01-29

Family

ID=13786637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8288278A Pending JPS5512506A (en) 1978-07-10 1978-07-10 Shift register circuit

Country Status (1)

Country Link
JP (1) JPS5512506A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605763A (en) * 1983-06-24 1985-01-12 Yaskawa Electric Mfg Co Ltd Winding of pole change induction motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS605763A (en) * 1983-06-24 1985-01-12 Yaskawa Electric Mfg Co Ltd Winding of pole change induction motor

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