JPS56127990A - Level control circuit - Google Patents

Level control circuit

Info

Publication number
JPS56127990A
JPS56127990A JP2790980A JP2790980A JPS56127990A JP S56127990 A JPS56127990 A JP S56127990A JP 2790980 A JP2790980 A JP 2790980A JP 2790980 A JP2790980 A JP 2790980A JP S56127990 A JPS56127990 A JP S56127990A
Authority
JP
Japan
Prior art keywords
voltage
control circuit
dividing circuit
level control
voltage dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2790980A
Other languages
Japanese (ja)
Inventor
Katsuyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP2790980A priority Critical patent/JPS56127990A/en
Publication of JPS56127990A publication Critical patent/JPS56127990A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

PURPOSE:To obtain a level control circuit than can realize a low power consumption and high-speed reading, by forming a voltage dividing circuit having a feedback function with the depression-type MISFET and others and limiting the voltage of a memory matrix input/output line at a certain level. CONSTITUTION:The common input/output line DCOM and anti-DCOM of the static memory cells 1a arranged in a matrix are connected to a voltage dividing circuit consisting of the depression-type MISFETQ17, Q18 and others that receive the voltage of the other end of the serial resistances R1 and R2 with one end connected to the source respectively. A feedback control is given to the conductance of each of the FETQ15 and Q17 which vary their bias diretions due to the variation of the voltage drop of the resistances R1 and R2 in accordance with the levels of the line CDM and anti-CDM corresponding to the storage contents of the selected cells 1a-. Thus the output impedance before the read signal is supplied to the voltage dividing circuit is increased to reduce the power consumption, and at the same time the input voltage is limited at a certain level by a low output impedance to realize a high-speed reading. Such level control circuit can be obtained.
JP2790980A 1980-03-07 1980-03-07 Level control circuit Pending JPS56127990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2790980A JPS56127990A (en) 1980-03-07 1980-03-07 Level control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2790980A JPS56127990A (en) 1980-03-07 1980-03-07 Level control circuit

Publications (1)

Publication Number Publication Date
JPS56127990A true JPS56127990A (en) 1981-10-07

Family

ID=12234002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2790980A Pending JPS56127990A (en) 1980-03-07 1980-03-07 Level control circuit

Country Status (1)

Country Link
JP (1) JPS56127990A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136097A (en) * 1983-12-23 1985-07-19 Hitachi Ltd Associative memory device
EP0319223A2 (en) * 1987-12-03 1989-06-07 Matsushita Electronics Corporation An output circuit system of static random access memory circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136097A (en) * 1983-12-23 1985-07-19 Hitachi Ltd Associative memory device
EP0319223A2 (en) * 1987-12-03 1989-06-07 Matsushita Electronics Corporation An output circuit system of static random access memory circuit

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