JPS56126316A - Mos comparing integrated circuit - Google Patents

Mos comparing integrated circuit

Info

Publication number
JPS56126316A
JPS56126316A JP2998980A JP2998980A JPS56126316A JP S56126316 A JPS56126316 A JP S56126316A JP 2998980 A JP2998980 A JP 2998980A JP 2998980 A JP2998980 A JP 2998980A JP S56126316 A JPS56126316 A JP S56126316A
Authority
JP
Japan
Prior art keywords
output
clock signal
low level
generator
mosts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2998980A
Other languages
Japanese (ja)
Inventor
Kazukiyo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2998980A priority Critical patent/JPS56126316A/en
Publication of JPS56126316A publication Critical patent/JPS56126316A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To realize a high-speed amplification and latching, by installing a means that clamps the output terminal of a differential amplifier after cancelling a latch mode. CONSTITUTION:When the output (a) of the 1st clock signal generator 31 is set at a low level, the latch mode of a latching circuit is cancelled. In this case, the output C of the 3rd clock signal generator 60 is set at a high level to turn on the MOSTs 42, 43 and 44. As a result, both the nodes (a) and (b) are set at the same potential. In the state II, the output (b) of the 2nd clock signal generator 63 is set at a low level to turn off the MOSTs 5 and 6. Thus the differential amplifier is set under an inactive state. In the state III, the output (c) of the generator 60 is set at a low level, and the output (b) of the generator 63 is set at a high level. Thus the MOSTs 5 and 6 are turned on to make the differential amplifier active, and accordingly the differential input to be applied to the terminals 102 and 103 can be amplified. The state III completes by a transition of the 2nd clock signal (b) to a low level. The 1st clock signal (a) is set at a high level as soon as the state III completes, and an amplified signal is latched.
JP2998980A 1980-03-10 1980-03-10 Mos comparing integrated circuit Pending JPS56126316A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2998980A JPS56126316A (en) 1980-03-10 1980-03-10 Mos comparing integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2998980A JPS56126316A (en) 1980-03-10 1980-03-10 Mos comparing integrated circuit

Publications (1)

Publication Number Publication Date
JPS56126316A true JPS56126316A (en) 1981-10-03

Family

ID=12291356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2998980A Pending JPS56126316A (en) 1980-03-10 1980-03-10 Mos comparing integrated circuit

Country Status (1)

Country Link
JP (1) JPS56126316A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639219A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd High speed comparator
JPH05218872A (en) * 1992-01-20 1993-08-27 Nec Corp Comparator circuit and driving method for the circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114840A (en) * 1973-02-14 1974-11-01
US4110639A (en) * 1976-12-09 1978-08-29 Texas Instruments Incorporated Address buffer circuit for high speed semiconductor memory
JPS54136267A (en) * 1978-04-14 1979-10-23 Nippon Telegr & Teleph Corp <Ntt> Data input circuit
JPS5520054A (en) * 1978-07-28 1980-02-13 Mitsubishi Electric Corp Differential amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114840A (en) * 1973-02-14 1974-11-01
US4110639A (en) * 1976-12-09 1978-08-29 Texas Instruments Incorporated Address buffer circuit for high speed semiconductor memory
JPS54136267A (en) * 1978-04-14 1979-10-23 Nippon Telegr & Teleph Corp <Ntt> Data input circuit
JPS5520054A (en) * 1978-07-28 1980-02-13 Mitsubishi Electric Corp Differential amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639219A (en) * 1986-06-30 1988-01-14 Fujitsu Ltd High speed comparator
JPH05218872A (en) * 1992-01-20 1993-08-27 Nec Corp Comparator circuit and driving method for the circuit

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