JPS56125132A - Code conversion system - Google Patents

Code conversion system

Info

Publication number
JPS56125132A
JPS56125132A JP2935780A JP2935780A JPS56125132A JP S56125132 A JPS56125132 A JP S56125132A JP 2935780 A JP2935780 A JP 2935780A JP 2935780 A JP2935780 A JP 2935780A JP S56125132 A JPS56125132 A JP S56125132A
Authority
JP
Japan
Prior art keywords
bit
data
bits
block
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2935780A
Other languages
Japanese (ja)
Inventor
Kyoji Koseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2935780A priority Critical patent/JPS56125132A/en
Publication of JPS56125132A publication Critical patent/JPS56125132A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To reduce the processing time for code conversion, by providing the conversion circuit converting a plurality of row data inputted in 8Xn -bit units to the column data of 8Xn -bits and the means adding the dummy bit to the BCH code input or output at the conversion circuit. CONSTITUTION:Shift registers 4, 5 and X-Y converter 6 are connected to the data bus 10 of a microprocessor unit MPU1 in addition to the nonvolatile memory RAM2, fixed memory ROM3, and the dummy code in 1-bit is added to the reception data RD, e.g., block every 7 bits, to constitute as the block every 8 bits and the result is once stored in the shift register 4. After that, the data of one block is shifted by sequentially switching it with the X-Y converter 6 to shift corresponding bit to each group, and the bit corresponding to each group is located to the shift register 5 and stored. At readout, the readout XY conversion is made in parallel.
JP2935780A 1980-03-08 1980-03-08 Code conversion system Pending JPS56125132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2935780A JPS56125132A (en) 1980-03-08 1980-03-08 Code conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2935780A JPS56125132A (en) 1980-03-08 1980-03-08 Code conversion system

Publications (1)

Publication Number Publication Date
JPS56125132A true JPS56125132A (en) 1981-10-01

Family

ID=12273938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2935780A Pending JPS56125132A (en) 1980-03-08 1980-03-08 Code conversion system

Country Status (1)

Country Link
JP (1) JPS56125132A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734707B2 (en) * 2002-01-11 2004-05-11 Samsung Electronics Co., Ltd. Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734707B2 (en) * 2002-01-11 2004-05-11 Samsung Electronics Co., Ltd. Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device

Similar Documents

Publication Publication Date Title
JPS56125132A (en) Code conversion system
KR920006843A (en) Semiconductor computing device
EP0153108A3 (en) Decimal digit processing apparatus
GB965749A (en) Improvements relating to devices for dividing numbers
CA1191211A (en) Electronic time switch
SU132434A1 (en) The method of converting binary code to decimal and device for its implementation
SU1091156A1 (en) Shifting device
SU922731A1 (en) Device for multiplying in residual class system
JPS56162564A (en) Multivalued code generator
SU363119A1 (en) REGISTER OF SHIFT
SU813446A1 (en) Device for solvingsystems of linear equations
SU1034036A1 (en) Device for squaring numbers by p modulus
SU1269271A1 (en) Binary code-to-residual class system code converter
JPS56114043A (en) Code converting circuit
JPS5776633A (en) Signal processor
SU374585A1 (en)
DE3374256D1 (en) Shift register arrangement and data transmission system comprising such an arrangement
SU798862A1 (en) Device for solving simultaneous linear equations
SU1001078A1 (en) Unit-counting code-to-binary code converter
SU424142A1 (en) DEVICE COMPARISON OF TWO NUMBERS IN DIGITAL CODE
RU2012135C1 (en) Code converter
SU959061A1 (en) Device for interfacing relay subscribers to computer
SU526884A1 (en) Code converter
SU596952A1 (en) Arrangement for solving differential simultaneous equations
JPS57705A (en) Operating method of ladder circuit input part on column cycle system