JPS56120135A - Manufacture of composite integrated circuit - Google Patents
Manufacture of composite integrated circuitInfo
- Publication number
- JPS56120135A JPS56120135A JP2354580A JP2354580A JPS56120135A JP S56120135 A JPS56120135 A JP S56120135A JP 2354580 A JP2354580 A JP 2354580A JP 2354580 A JP2354580 A JP 2354580A JP S56120135 A JPS56120135 A JP S56120135A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- split
- composite integrated
- split groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
PURPOSE:To provide highly packed mounting and miniaturization by soldering mountings including external terminals on a substrate, coating the substrate with silicon resin, curing through drying and splitting it along a split groove. CONSTITUTION:A substrate 1 contains a blook 1-a formed in such pattern as to have the effective function of a composite integrated circuit and the edge 1-b of the substrate itself. On this substrate 1, mounting parts 3 including esternal therminals are mounted with solder on each block 1-a. Next, the substrate 1 is coated over together with mounting parts 3 by means of silicon resin 2 modified at viscosity of approximately 3,000 centipoise. Then the coat is cured through drying in an atmosphere at 101-150 deg.C. Later the processed substrate 1 is split by a split groove preset along a boundary 1-c. The resin 2 is also split almost vertically with the split groove, thus providing a completed composite integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2354580A JPS56120135A (en) | 1980-02-27 | 1980-02-27 | Manufacture of composite integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2354580A JPS56120135A (en) | 1980-02-27 | 1980-02-27 | Manufacture of composite integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56120135A true JPS56120135A (en) | 1981-09-21 |
Family
ID=12113437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2354580A Pending JPS56120135A (en) | 1980-02-27 | 1980-02-27 | Manufacture of composite integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56120135A (en) |
-
1980
- 1980-02-27 JP JP2354580A patent/JPS56120135A/en active Pending
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