JPS56115024A - Automatic threshold level setting circuit - Google Patents

Automatic threshold level setting circuit

Info

Publication number
JPS56115024A
JPS56115024A JP1729680A JP1729680A JPS56115024A JP S56115024 A JPS56115024 A JP S56115024A JP 1729680 A JP1729680 A JP 1729680A JP 1729680 A JP1729680 A JP 1729680A JP S56115024 A JPS56115024 A JP S56115024A
Authority
JP
Japan
Prior art keywords
input signal
threshold level
maximum
fluctuation
minimum values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1729680A
Other languages
Japanese (ja)
Inventor
Nobumi Kuriyama
Takeshi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1729680A priority Critical patent/JPS56115024A/en
Publication of JPS56115024A publication Critical patent/JPS56115024A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To set the threshold level at the optimum value following the DC level as well as the amplitude of an input signal, by detecting both the maximum and minimum values of the input signal and thus using the mean value of these maximum and minimum values for the comparing threshold level to the input signal. CONSTITUTION:The input signal is applied to the input terminal 23 of the comparator 22 as well as to both the maximum and minimum value detector circuits 25 and 26 each to detect the maximum and minimum values of the input signal. The mean value detector circuit 27 averages the supplied maximum and minimum values of the input signal to use the mean value for the reference voltage of the circuit 22. Thus the threshold level has a fluctuation by the same value although the amplitude of the input signal has a fluctuation and the DC level of the input signal has a fluctuation. As a result, the threshold level is always set at 1/2 the input amplitude, and thus a fluctuation can be prevented for the duration of the output pulse.
JP1729680A 1980-02-15 1980-02-15 Automatic threshold level setting circuit Pending JPS56115024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1729680A JPS56115024A (en) 1980-02-15 1980-02-15 Automatic threshold level setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1729680A JPS56115024A (en) 1980-02-15 1980-02-15 Automatic threshold level setting circuit

Publications (1)

Publication Number Publication Date
JPS56115024A true JPS56115024A (en) 1981-09-10

Family

ID=11940027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1729680A Pending JPS56115024A (en) 1980-02-15 1980-02-15 Automatic threshold level setting circuit

Country Status (1)

Country Link
JP (1) JPS56115024A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0186324U (en) * 1987-11-27 1989-06-07
WO1990006578A1 (en) * 1988-11-25 1990-06-14 Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg Process for recovering a coded signal sequence
EP0602697A1 (en) * 1992-12-14 1994-06-22 Delco Electronics Corporation Analogue to digital converter
EP0684455A1 (en) * 1994-05-27 1995-11-29 Snr Roulements Interpolation circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356918A (en) * 1976-11-01 1978-05-23 Oki Electric Ind Co Ltd Picture read system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356918A (en) * 1976-11-01 1978-05-23 Oki Electric Ind Co Ltd Picture read system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0186324U (en) * 1987-11-27 1989-06-07
WO1990006578A1 (en) * 1988-11-25 1990-06-14 Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg Process for recovering a coded signal sequence
EP0602697A1 (en) * 1992-12-14 1994-06-22 Delco Electronics Corporation Analogue to digital converter
EP0684455A1 (en) * 1994-05-27 1995-11-29 Snr Roulements Interpolation circuit

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