JPS56114071A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS56114071A
JPS56114071A JP1637380A JP1637380A JPS56114071A JP S56114071 A JPS56114071 A JP S56114071A JP 1637380 A JP1637380 A JP 1637380A JP 1637380 A JP1637380 A JP 1637380A JP S56114071 A JPS56114071 A JP S56114071A
Authority
JP
Japan
Prior art keywords
overflow
detector
arithmetic circuit
output
additions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1637380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6131488B2 (enrdf_load_stackoverflow
Inventor
Yuichi Kawakami
Takao Nishitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1637380A priority Critical patent/JPS56114071A/ja
Publication of JPS56114071A publication Critical patent/JPS56114071A/ja
Publication of JPS6131488B2 publication Critical patent/JPS6131488B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP1637380A 1980-02-13 1980-02-13 Arithmetic circuit Granted JPS56114071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1637380A JPS56114071A (en) 1980-02-13 1980-02-13 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1637380A JPS56114071A (en) 1980-02-13 1980-02-13 Arithmetic circuit

Publications (2)

Publication Number Publication Date
JPS56114071A true JPS56114071A (en) 1981-09-08
JPS6131488B2 JPS6131488B2 (enrdf_load_stackoverflow) 1986-07-21

Family

ID=11914488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1637380A Granted JPS56114071A (en) 1980-02-13 1980-02-13 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS56114071A (enrdf_load_stackoverflow)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215633A (ja) * 1985-07-12 1987-01-24 シ−メンス、アクチエンゲゼルシヤフト キヤリ・セイブ加算器を有する装置
JPS63263909A (ja) * 1987-04-22 1988-10-31 Victor Co Of Japan Ltd デジタル信号の演算装置におけるオ−バ−ロ−ド防止用ピ−ク表示装置
JPS63292716A (ja) * 1987-05-25 1988-11-30 Victor Co Of Japan Ltd デジタル信号の演算装置におけるオ−バ−ロ−ド防止用ピ−ク表示装置
JPH02189026A (ja) * 1989-01-17 1990-07-25 Mitsubishi Electric Corp カウンタのオーバフロー及びアンダフロー検出装置
JPH02222318A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk ディジタルフィルタを用いた演算装置
JPH02222319A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk ディジタルフィルタ
JPH02222317A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk デジタルフィルタ

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215633A (ja) * 1985-07-12 1987-01-24 シ−メンス、アクチエンゲゼルシヤフト キヤリ・セイブ加算器を有する装置
JPS63263909A (ja) * 1987-04-22 1988-10-31 Victor Co Of Japan Ltd デジタル信号の演算装置におけるオ−バ−ロ−ド防止用ピ−ク表示装置
JPS63292716A (ja) * 1987-05-25 1988-11-30 Victor Co Of Japan Ltd デジタル信号の演算装置におけるオ−バ−ロ−ド防止用ピ−ク表示装置
JPH02189026A (ja) * 1989-01-17 1990-07-25 Mitsubishi Electric Corp カウンタのオーバフロー及びアンダフロー検出装置
JPH02222318A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk ディジタルフィルタを用いた演算装置
JPH02222319A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk ディジタルフィルタ
JPH02222317A (ja) * 1989-02-23 1990-09-05 Lsi Rojitsuku Kk デジタルフィルタ

Also Published As

Publication number Publication date
JPS6131488B2 (enrdf_load_stackoverflow) 1986-07-21

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