JPS56114024A - Synchronous pulse generator - Google Patents
Synchronous pulse generatorInfo
- Publication number
- JPS56114024A JPS56114024A JP1637680A JP1637680A JPS56114024A JP S56114024 A JPS56114024 A JP S56114024A JP 1637680 A JP1637680 A JP 1637680A JP 1637680 A JP1637680 A JP 1637680A JP S56114024 A JPS56114024 A JP S56114024A
- Authority
- JP
- Japan
- Prior art keywords
- output
- pulse
- synchronous
- input pulse
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To obtain a synchronous pulse generator that is free from any malfunction even with a high-speed input pulse and is suited for an integration, by producing the synchronous pulse synchronizing with the clock pulse CLP through a synchronous means after counting the asynchronous pulses up to a prescribed number. CONSTITUTION:The asynchronous input pulse signal of 8 pulses is applied to the terminal A of the T-type FF1. The waveforms are shown in the diagram respectively for the T-type FF1-3 and 9, the D-type latches D-L6 and 7 plus the outputs B-D, J, G, H and I of the AND gate 8 each. At the moment when the output D changes to the level L from H with the 8th pulse, the FF9 is set. The output J turns to ''H'' from ''L'', and the output of D-L6 delivers ''H'' with the timing of CLPphi2 within a computer. Then the output of D-L7 delivers ''H'' with the timing of CLPphi1. Thus the input pulse count end signal synchronous with phi1 is obtained. Then the output I becomes ''H'' as soon as the output of D-L7 becomes ''H'', and the initialization is given to the FF1-3 and 9. Thus the counting is possible for the next input pulse.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55016376A JPS6019822B2 (en) | 1980-02-13 | 1980-02-13 | Synchronous pulse generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55016376A JPS6019822B2 (en) | 1980-02-13 | 1980-02-13 | Synchronous pulse generator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56114024A true JPS56114024A (en) | 1981-09-08 |
JPS6019822B2 JPS6019822B2 (en) | 1985-05-18 |
Family
ID=11914563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55016376A Expired JPS6019822B2 (en) | 1980-02-13 | 1980-02-13 | Synchronous pulse generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019822B2 (en) |
-
1980
- 1980-02-13 JP JP55016376A patent/JPS6019822B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6019822B2 (en) | 1985-05-18 |
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