JPS56110258A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56110258A
JPS56110258A JP1151580A JP1151580A JPS56110258A JP S56110258 A JPS56110258 A JP S56110258A JP 1151580 A JP1151580 A JP 1151580A JP 1151580 A JP1151580 A JP 1151580A JP S56110258 A JPS56110258 A JP S56110258A
Authority
JP
Japan
Prior art keywords
diode
electrically connected
amplitude
circuit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1151580A
Other languages
Japanese (ja)
Inventor
Yasusuke Yamamoto
Hiroshi Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1151580A priority Critical patent/JPS56110258A/en
Publication of JPS56110258A publication Critical patent/JPS56110258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To match logic amplitude with CML circuit by using a diode which is capable of freely controlling an ideal factor n as a load on a logic circuit and a memory circuit and clarifying the relationship between the ideal factor n of a diode and an amplitude factor beta. CONSTITUTION:Each collector 5 of transistor T1, T2, T3 and each cathode 6 of diode D1, D2, D3 are electrically connected together. Then the pluse terminal of a power supply 1 and anodes on the diodes D1, D2, D3 are electrically connected to each other. In addition, emitters 8 of the transistors T1, T2, T3 are electrically connected to one terminal of the power supply 1. In order to carry out the stable operation of the logic circuit, a diode and a transistor having n value and amplitude factor beta equivalent to the value of (n k T/q)lnbeta>0.25V are used.
JP1151580A 1980-02-04 1980-02-04 Semiconductor device Pending JPS56110258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1151580A JPS56110258A (en) 1980-02-04 1980-02-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1151580A JPS56110258A (en) 1980-02-04 1980-02-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56110258A true JPS56110258A (en) 1981-09-01

Family

ID=11780131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1151580A Pending JPS56110258A (en) 1980-02-04 1980-02-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56110258A (en)

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