JPS56107386A - Isolation gate fet memory - Google Patents

Isolation gate fet memory

Info

Publication number
JPS56107386A
JPS56107386A JP958280A JP958280A JPS56107386A JP S56107386 A JPS56107386 A JP S56107386A JP 958280 A JP958280 A JP 958280A JP 958280 A JP958280 A JP 958280A JP S56107386 A JPS56107386 A JP S56107386A
Authority
JP
Japan
Prior art keywords
circuit
grounding
clamper
ground line
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP958280A
Other languages
Japanese (ja)
Inventor
Hirotoshi Sawada
Nobuaki Ieda
Tsuneo Mano
Tatsuo Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP958280A priority Critical patent/JPS56107386A/en
Publication of JPS56107386A publication Critical patent/JPS56107386A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

PURPOSE:To ensure the grounding of clamper circuit, by connecting the ground line of word line clamper circuit to the ground pad or its vicinity as wirting independent from other ground lines. CONSTITUTION:At the both ends or one end of the word line WL of memory cell array, clamper circuits CL1, CL2 are connected, and grounding of both or one end of CL1, CL2 is not connected to the ground line G1 of other circuit but to exclusive use independent wiring G2 and connected to the grounding pad P1 or its vicinity. With this constitution, even if greater current flows to the ground line connected to other circuit, the variance of potential of the ground line does not the potential of ground line exclusive for the clamper circuit, then the grounding of clamper circuit is ensured. Thus, since the clamp function is not interferred and no care about the relinquish of memory information of memory cells is required.
JP958280A 1980-01-30 1980-01-30 Isolation gate fet memory Pending JPS56107386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP958280A JPS56107386A (en) 1980-01-30 1980-01-30 Isolation gate fet memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP958280A JPS56107386A (en) 1980-01-30 1980-01-30 Isolation gate fet memory

Publications (1)

Publication Number Publication Date
JPS56107386A true JPS56107386A (en) 1981-08-26

Family

ID=11724298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP958280A Pending JPS56107386A (en) 1980-01-30 1980-01-30 Isolation gate fet memory

Country Status (1)

Country Link
JP (1) JPS56107386A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114392A (en) * 1981-12-07 1983-07-07 Fujitsu Ltd Semiconductor storage device
JPS593788A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semicondutor storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114392A (en) * 1981-12-07 1983-07-07 Fujitsu Ltd Semiconductor storage device
JPS593788A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semicondutor storage device

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