JPS56105398A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56105398A
JPS56105398A JP653280A JP653280A JPS56105398A JP S56105398 A JPS56105398 A JP S56105398A JP 653280 A JP653280 A JP 653280A JP 653280 A JP653280 A JP 653280A JP S56105398 A JPS56105398 A JP S56105398A
Authority
JP
Japan
Prior art keywords
unit
bus
circuit
output
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP653280A
Other languages
Japanese (ja)
Inventor
Yasuo Omori
Hiroshi Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP653280A priority Critical patent/JPS56105398A/en
Publication of JPS56105398A publication Critical patent/JPS56105398A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the influence of the defect of a single unit, by providing every building-blocked semiconductor unit connected to the common bus with a signal monitor circuit and by disconnecting the defective unit from the common bus. CONSTITUTION:Unit U which is built up and is connected to common addess control I/O bus AD, control bus CT, and data I/O bus I/O is provided with signal monitor circuit M. If anomaly occurs in one, at least, of main clock phiE which passes through unit selecting circuit E at the stand-by period, internal clocks phii and phij output from internal clock signal generating circuit phi, and so on to invert the level, the output of OR gate O is inverted to the high level through NAND gate N. Then, AND gate Ai... are formed by low-level output (m) of circuit M, and data I/O, address, decoder, memory cell, and sense system circuits D, B and C are made inactive, and the defective unit is disconnected automatically from the common bus and does not consume undesired power, and thus, the influence of the defect of the single unit is prevented.
JP653280A 1980-01-23 1980-01-23 Semiconductor device Pending JPS56105398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP653280A JPS56105398A (en) 1980-01-23 1980-01-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP653280A JPS56105398A (en) 1980-01-23 1980-01-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56105398A true JPS56105398A (en) 1981-08-21

Family

ID=11640959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP653280A Pending JPS56105398A (en) 1980-01-23 1980-01-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56105398A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639133A (en) * 1986-06-27 1988-01-14 エツセジ−エツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Method of designing integrated microcomputer and integrated microcomputer with module construction obtained by the method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639133A (en) * 1986-06-27 1988-01-14 エツセジ−エツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Method of designing integrated microcomputer and integrated microcomputer with module construction obtained by the method
JPH0812900B2 (en) * 1986-06-27 1996-02-07 エツセジ−エツセ ミクロエレツトロニカ ソチエタ ペル アノニマ 1-chip microcomputer manufacturing method and 1-chip microcomputer manufactured by the method

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