JPH03252998A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the operation time and to reduce the current consumption by providing an address decoding means and a skip means which is set to the first set state for operation of a discriminating means or the second state for non-operation of the discriminating means. CONSTITUTION:In the second set state, no defective memory cells exist, and a line 21 to transmit the select signal from a redundant address discriminating circuit 3 to a row decoder 1 is inactivated. A start pulse is directly inputted to a word line boosting circuit 8 from a redundant skip circuit 6through lines 22 and 24. Consequently, the time required for selection of a word line 2 is shortened in comparison with that of a conventional semiconductor memory device in the second set state. Since the redundant address discriminating circuit 3 is not operated, the power consumption due to the circuit 3 is considerably reduced. Thus, the operation speed is increased by the time required for the discriminating operation of the discriminating means, and the power consumption of the discriminating means is suppressed to reduce the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly relates to an improvement of a semiconductor memory device having a redundant circuit.

(Prior Art) In semiconductor memory devices such as DRAMs and SRAMs, it is difficult to avoid the occurrence of some defective memory cells during the manufacturing stage. Therefore, generally, a redundant circuit including redundant memory cells for replacing defective memory cells is provided in a semiconductor memory device.

FIG. 3 shows the main parts of a conventional semiconductor memory device.

Word line 2 connected to regular memory cells (not shown)
0 is connected to the row decoder 10. On the other hand, a redundant address determination circuit 30 is connected to a redundant word line 40 connected to a redundant memory cell (not shown) for relieving a defective memory cell. The redundant address determination circuit 30 determines whether the input row address is an address to be redundantly repaired, that is, whether the row address is the address of a memory cell to be replaced by a redundant memory cell. Redundant address determination circuit 30 supplies a selection signal for activating row decoder 10 to row decoder IO via line 90 when the input row address is not an address to be redundantly repaired.

If a defective memory cell is detected during post-manufacturing inspection of this semiconductor memory device, a redundant memory cell will be selected in place of the defective memory cell when an address specifying the defective memory cell is input. , the redundant address determination circuit 30 is set.

The redundant address determination circuit 30 starts operating in response to a start pulse from the row start trigger circuit 50. The row decoder 10 and the redundant address determination circuit 30 have the word line 20 or redundant word selected by them;
A word line booster circuit 80 for driving 1140 is connected. The word line booster circuit 80 includes a delay circuit 7.
A start pulse from the row start trigger circuit 50 is input via 0. The delay circuit 70 provides a delay to the start pulse corresponding to the time required for the determination by the redundant address determination circuit 30, and synchronizes the timing of the operation of the word line booster circuit 80 and the operation of the row decoder 10.

(Problems to be Solved by the Invention) In the configuration of the conventional semiconductor memory device described above, there are no defective memory cells at all, and even in a semiconductor memory device in which redundant memory cells are not used, the input address is the redundant address. Processed by the determination circuit 30. Therefore, unnecessary power is consumed by the redundant address determination circuit 30.

Further, even in a semiconductor memory device in which redundant memory cells are not used, the time required for address decoding increases by the time required for the operation of redundant address determination circuit 30.

The present invention was made in view of the current situation, and
The purpose is to provide a semiconductor memory device that can shorten operating time and reduce current consumption when there are no defective memory cells and redundant memory cells are not used. .

(Means for Solving the Problems) A semiconductor memory device of the present invention includes a redundant circuit including means for determining whether an input address is an address to be redundantly repaired, and an address for decoding the input address. The decoding means is connected to the determining means and the address decoding means, and is in one of two setting states: a first setting state in which the determining means is operated and a second setting state in which the determining means is not operated. and skip means set to the first setting state, and the address decoding means determines whether the input address is a target of redundancy relief when the skip means is set to the first setting state. If the skip means is set to the second setting state, it is activated by a signal from the skip means, thereby causing the above-mentioned The purpose is achieved.

(Function) In the semiconductor memory device of the present invention, when the skipping means is set to the first setting state, the determining means determines whether the manually-operated address is an address to be redundantly saved. If it is determined that the input address is not an address to be redundantly repaired, the determination means outputs a selection signal and the address decoding means is activated.

On the other hand, when the skip means is set to the second setting state, the determination means does not operate and the address decoding means is directly activated by a signal from the skip means.

Therefore, according to the present invention, for a semiconductor memory device in which there is no defect and does not require redundancy relief, the skip means is set to the second setting state, thereby reducing the time spent on the determination operation of the determination means. The power consumption of the determination means can be suppressed.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows a main part of an embodiment of the present invention. In this example,
Similar to the conventional semiconductor memory device (FIG. 3), there are word lines 2 connected to normal memory cells (not shown) and redundant memory cells (not shown) for relieving defective memory cells.
and a redundant word line 4 connected to the redundant word line 4. Word line 2 is a row decoder l for decoding row addresses.
On the other hand, the redundant word line 4 is connected to the redundant address determination circuit 3. The redundant address determination circuit 3 is
It is determined whether the input row address is an address targeted for redundancy relief, that is, whether it is an address of a memory cell to be replaced by a redundant memory cell. The redundant address determination circuit 3 sends a selection signal to the row decoder via a line 21 to activate the row decoder 1 to start decoding the row address when the input row address is not an address to be redundantly repaired. Give to 1. The row decoder 1 also starts operating when pulses are input via lines 22 and 23. A word line booster circuit 8 is connected to the row decoder 1 and redundant address determination circuit 3 for driving the word line 2 or redundant word line 4 selected by them.

The row start trigger circuit 5 redundantly skips the start pulse for starting the circuit described above.

is applied to the block circuit 6. The redundancy skip circuit 6 is set to one of two setting states based on the result of the memory cell test.

The first setting state is for a semiconductor memory device in which a defective memory cell exists and it is necessary to replace the defective memory cell with a redundant memory cell. In the first setting state, redundancy skip circuit 6 transmits a start pulse from row start trigger circuit 5 to redundant address determination circuit 3 and delay circuit 7 via lines 25 and 26, respectively. The start pulse delayed by a predetermined time by the delay circuit 7 is input to the word line booster circuit 8 via a line 27 . Also, a line 22 connecting the redundant skip circuit 6 to the row decoder 1 and the word line booster circuit 8
．． 23 and 24 are inactivated. In the first setting state, the redundant address determination circuit 3, row decoder 1, and word line booster circuit 8 operate in the same manner as in the prior art.

The second setting state is for a semiconductor memory device in which there are no defective memory cells and redundancy relief using redundant memory cells is not necessary. In the second setting state, no start pulse is given to the redundant address determination circuit 3, and therefore,
Redundant address determination circuit 3 does not operate. Line 21 for transmitting the selection signal from redundant address determination circuit 3 to row decoder 1 is inactivated. Word line booster circuit 8
is connected via lines 22 and 24 to redundant skip circuit 6.
A start pulse is input directly from Also, row decoder l is activated directly by a start pulse applied from redundant skip circuit 6 via lines 22 and 23. As can be seen from the above description, in the second setting state, after the start pulse is output from the row start trigger circuit 5, the row decoder 1 and the word line booster circuit 8 works. Therefore, in the second setting state, the time required to select the word line 2 is shorter than in the conventional semiconductor memory device. Further, since the redundant address determination circuit 3 does not operate, the power consumption by the circuit 3 is significantly suppressed, and the overall power consumption of the semiconductor memory device is also reduced.

In this embodiment, a semiconductor memory device in which redundancy relief is performed line by line in the row direction is shown, but in a semiconductor memory device in which redundancy relief is performed not only in the row direction but also in line units in the column direction. It is also possible to provide a redundant skip circuit for directly activating the column decoder by skipping the redundant address determination circuit for column addresses.

The detailed configuration of the redundant skip circuit 6 will be explained with reference to FIG. The lines in FIG. 2 do not necessarily correspond exactly to the lines in FIG. 1 because FIG. 1 schematically shows this embodiment.

The state setting of the redundant skip circuit 6 is based on the drain of the p-channel transistor 601 and the n-channel transistor 602.
This is determined by whether or not the fuse 603 provided between the drain and the fuse 603 is cut. When setting the redundant skip circuit 6 to the first setting state in which the redundant address determination circuit 3 is operated, the fuse 603 is cut off. p-channel transistor 601 and n-channel transistor 602
A power-on signal PON is applied to the gate of. n
A latch circuit 604 having two inverters is connected between the channel transistor 602 and the fuse 603. The output of the latch circuit 604 is applied to one input terminal of a NOR gate 605 and the gate of a p-channel transistor 606 provided on the output side of the NOR gate 605. The output of the latch circuit 604 is also inverted by an inverter 607, and the inverted signal connects the delay circuit 7 and the word line boost circuit 8.
Input to the gate of channel transistor 608, the gate of p-channel transistor 609 that connects row start trigger circuit 5 and redundant address determination circuit 3, and the gate of p-channel transistor 61O that connects redundant address determination circuit 3 and row decoder l. has been done. The other input terminal of the NOR gate 605 is connected to the row start trigger circuit 5. p-channel transistor 60
The output side of 6 is a word line booster circuit 8 and a row decoder l.
It is connected to the.

The power-on signal PON becomes low level when the power is turned on. When fuse 603 is disconnected (first setting state), p-channel transistor 601 and n-channel transistor 602 are separated, so
The output of latch circuit 604 becomes high level. Therefore,
The p-channel transistors 608, 609 and 610 are turned on, and the redundancy function realized by the redundant address determination circuit 3 and the like becomes effective. Low start trigger circuit 5 to N
The input to OR gate 605 is blocked by NOR gate 605. Furthermore, p-channel transistor 60
6 is off.

When fuse 603 is not cut (second setting state), p-channel transistor 601 and n
Since the channel transistor 602 constitutes an inverter, the output of the latch circuit 604 becomes low level when the power is turned on. Therefore, three p-channel transistors 60
8.609 and 610 are turned off, and the redundant address determination circuit 3 does not operate. Since one input of the NOR gate 605 is at a low level and the p-channel transistor 606 is turned on, the start pulse from the row start trigger circuit 5 passes through the NOR gate 605 and the p-channel transistor 606 and is output to the row decoder 1 and the p-channel transistor 606. It is directly input to the word line booster circuit 8.

In the circuit of FIG. 2, the p-channel transistor 608 on the output side of delay circuit 7 may be provided on the input side of delay circuit 7.

(Effects of the Invention) In the semiconductor memory device of the present invention, for products that do not require the use of a redundant circuit, by appropriately setting the skip means, it is possible to determine whether an input address is an address to be redundantly repaired. The means for this may be rendered inoperable. Therefore, a semiconductor memory device is provided in which the operation speed is increased by the time required for the determination operation in the determination means, and the power consumption of the determination means is suppressed, thereby reducing power consumption.

4. Figure 1 is a diagram schematically showing the main part of an embodiment of the present invention, Figure 2 is a circuit diagram showing the redundant skip circuit of the embodiment in more detail, and Figure 3 is a circuit diagram of the conventional redundant skip circuit. FIG. 2 is a diagram schematically showing a main part of an example of a semiconductor device.

l... Row decoder, 2... Word line, 3... Redundant address determination circuit, 4... Redundant word line, 5...
Low start trigger circuit, 6...redundant skip circuit,
7...Delay circuit, 8...Word line booster circuit.

that's all

Claims (1)

[Claims] 1) A redundant circuit including means for determining whether an input address is an address to be redundantly repaired, an address decoding means for decoding the input address, the determining means and the redundant circuit. Skip means is connected to the address decoding means and is set to one of two setting states: a first setting state in which the determining means is operated and a second setting state in which the determining means is not operated. When the skipping means is set to the first setting state, the address decoding means outputs an address when the determining means determines that the input address is not a target address for redundancy relief. A semiconductor memory device activated by a selection signal and activated by a signal from the skip means when the skip means is set to the second setting state.