JPS56103726A - Control system of bus - Google Patents

Control system of bus

Info

Publication number
JPS56103726A
JPS56103726A JP550680A JP550680A JPS56103726A JP S56103726 A JPS56103726 A JP S56103726A JP 550680 A JP550680 A JP 550680A JP 550680 A JP550680 A JP 550680A JP S56103726 A JPS56103726 A JP S56103726A
Authority
JP
Japan
Prior art keywords
processor
control section
buses
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP550680A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6215903B2 (enrdf_load_html_response
Inventor
Shiro Oishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP550680A priority Critical patent/JPS56103726A/ja
Publication of JPS56103726A publication Critical patent/JPS56103726A/ja
Publication of JPS6215903B2 publication Critical patent/JPS6215903B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
JP550680A 1980-01-21 1980-01-21 Control system of bus Granted JPS56103726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP550680A JPS56103726A (en) 1980-01-21 1980-01-21 Control system of bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP550680A JPS56103726A (en) 1980-01-21 1980-01-21 Control system of bus

Publications (2)

Publication Number Publication Date
JPS56103726A true JPS56103726A (en) 1981-08-19
JPS6215903B2 JPS6215903B2 (enrdf_load_html_response) 1987-04-09

Family

ID=11613077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP550680A Granted JPS56103726A (en) 1980-01-21 1980-01-21 Control system of bus

Country Status (1)

Country Link
JP (1) JPS56103726A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPS6215903B2 (enrdf_load_html_response) 1987-04-09

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