JPS56103455A - Semiconductor ic device - Google Patents

Semiconductor ic device

Info

Publication number
JPS56103455A
JPS56103455A JP600780A JP600780A JPS56103455A JP S56103455 A JPS56103455 A JP S56103455A JP 600780 A JP600780 A JP 600780A JP 600780 A JP600780 A JP 600780A JP S56103455 A JPS56103455 A JP S56103455A
Authority
JP
Japan
Prior art keywords
pads
lsi
projecting electrodes
chips
heating value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP600780A
Other languages
Japanese (ja)
Other versions
JPH0127582B2 (en
Inventor
Kenichi Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP600780A priority Critical patent/JPS56103455A/en
Publication of JPS56103455A publication Critical patent/JPS56103455A/en
Publication of JPH0127582B2 publication Critical patent/JPH0127582B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To make LSI operations be speeded up by minimizing a heat resistance by a method wherein semiconductor multilayer wiring chips and LSI chips are connected with each other through projecting electrodes for connection fitted on the respectively faced surfaces to each other, the LSI chips side is fixed on a ceramic substrate and a cooling tube are closely attached on the reverse of the substrate. CONSTITUTION:The projecting electrodes 12a, 12b for electrical connections and pads are formed on the surfaces of the LSI elements 10a, 10b respectively large in heating value, on which a transistors, resistors and wirings etc. of a high speed ligical circuit and the like are arranged. The projecting electrodes 13a, 13b for connections and the pads are formed as well on the bottom surfaces of semiconductor multilayer wiring chips 11a and 11b small in heating value which are connected to the projecting electrodes 12a, 12b are the pads, and the electrodes 12a, 12b and 13a, 13b respectively are attached to each other and the pads are connected in common using a wire 16. Subsequently, the reverse sides of the elements 10a, 10b are fixed to the ceramic substrate 14 and the cooling tube 18 having a through opening 19 through which a cooling medium is flowed is fixed to the reverse of the substrate 14. Thus, the heating value in the circuit is increased to obtain a high speed.
JP600780A 1980-01-22 1980-01-22 Semiconductor ic device Granted JPS56103455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP600780A JPS56103455A (en) 1980-01-22 1980-01-22 Semiconductor ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP600780A JPS56103455A (en) 1980-01-22 1980-01-22 Semiconductor ic device

Publications (2)

Publication Number Publication Date
JPS56103455A true JPS56103455A (en) 1981-08-18
JPH0127582B2 JPH0127582B2 (en) 1989-05-30

Family

ID=11626663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP600780A Granted JPS56103455A (en) 1980-01-22 1980-01-22 Semiconductor ic device

Country Status (1)

Country Link
JP (1) JPS56103455A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
US9731887B2 (en) 2012-02-24 2017-08-15 Boru International Co. Ltd. Rubber seal for vacuum receptacle and lid for the receptacle using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51102566A (en) * 1975-03-07 1976-09-10 Suwa Seikosha Kk Shusekikairo
JPS5394075U (en) * 1976-12-28 1978-08-01

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51102566A (en) * 1975-03-07 1976-09-10 Suwa Seikosha Kk Shusekikairo
JPS5394075U (en) * 1976-12-28 1978-08-01

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892230A (en) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp Semiconductor device
JPS6347259B2 (en) * 1981-11-27 1988-09-21 Mitsubishi Electric Corp
US9731887B2 (en) 2012-02-24 2017-08-15 Boru International Co. Ltd. Rubber seal for vacuum receptacle and lid for the receptacle using the same

Also Published As

Publication number Publication date
JPH0127582B2 (en) 1989-05-30

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