JPS5597758A - Synchronous detection circuit - Google Patents

Synchronous detection circuit

Info

Publication number
JPS5597758A
JPS5597758A JP630479A JP630479A JPS5597758A JP S5597758 A JPS5597758 A JP S5597758A JP 630479 A JP630479 A JP 630479A JP 630479 A JP630479 A JP 630479A JP S5597758 A JPS5597758 A JP S5597758A
Authority
JP
Japan
Prior art keywords
signal
frame
word
counter
synchronizing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP630479A
Other languages
Japanese (ja)
Inventor
Hiroshi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP630479A priority Critical patent/JPS5597758A/en
Publication of JPS5597758A publication Critical patent/JPS5597758A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Optical Recording Or Reproduction (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To improve the recording density of a PCM signal on a recording medium by carrying error detection and correction into effect after passing a bit clock signal, extracted by a clock generating circuit, through a frame counter and word counter. CONSTITUTION:Binary reproduced data which never includes a frame-synchronizing signal or word-synchronizing signal is supplied to terminal 1 and clock generating circuit 2 extracts bit clocks. This signal is passed through frame counter 8 and word counter 9 to generate three word timing pulses Sw in each frame, and after error detection correction 5 and D/A conversion 6, right and left channel signals of a stereo audio signal are led out from output terminals 7L and 7R. Consequently, the need to insert a frame-synchronizing signal into data is eliminated, so that the recording density of a PCM signal on a recording medium such as a rotary disk can be improved.
JP630479A 1979-01-22 1979-01-22 Synchronous detection circuit Pending JPS5597758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP630479A JPS5597758A (en) 1979-01-22 1979-01-22 Synchronous detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP630479A JPS5597758A (en) 1979-01-22 1979-01-22 Synchronous detection circuit

Publications (1)

Publication Number Publication Date
JPS5597758A true JPS5597758A (en) 1980-07-25

Family

ID=11634626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP630479A Pending JPS5597758A (en) 1979-01-22 1979-01-22 Synchronous detection circuit

Country Status (1)

Country Link
JP (1) JPS5597758A (en)

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