JPS5597091A - Bistable nonvolatile memory circuit - Google Patents

Bistable nonvolatile memory circuit

Info

Publication number
JPS5597091A
JPS5597091A JP362579A JP362579A JPS5597091A JP S5597091 A JPS5597091 A JP S5597091A JP 362579 A JP362579 A JP 362579A JP 362579 A JP362579 A JP 362579A JP S5597091 A JPS5597091 A JP S5597091A
Authority
JP
Japan
Prior art keywords
fet
line
memory
information
nonvolatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP362579A
Other languages
Japanese (ja)
Inventor
Etsuro Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP362579A priority Critical patent/JPS5597091A/en
Publication of JPS5597091A publication Critical patent/JPS5597091A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To stabilize the erasing action of the memory information by inserting MNOS memory FET into each signal feedback line of the bistable multivibrator and then connecting the FET in which the gate is connected to the common signal line in parallel to the MNOS memory FET. CONSTITUTION:The sources of switching enhansment-type MOSFET-T1 and T2 are connected to earth line 9; the drains are connected to the sources of load depression type MOSFET-T9 and T10; and the gates are connected to MNOS memory FET-MT13 and MT14 to which voltage MG of control line 11 is supplied in common. And the drains of MT13 and MT14 are connected to connection points A and B. At the same time, enhancement-type FET-T11 and T12 are connected in parallel to MT13 and MT14, and common signal line 12 is connected to the gates of T11 and T12 each. When T11 and T12 are turned on with the prescribed voltage, the information of the bistable multivibrator comprising T1, T2, T9, T10, MT13 and MT14 each is written into MT13 and MT14. And if the prescribed voltage is applied to line 11, the memory information is erased.
JP362579A 1979-01-16 1979-01-16 Bistable nonvolatile memory circuit Pending JPS5597091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP362579A JPS5597091A (en) 1979-01-16 1979-01-16 Bistable nonvolatile memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP362579A JPS5597091A (en) 1979-01-16 1979-01-16 Bistable nonvolatile memory circuit

Publications (1)

Publication Number Publication Date
JPS5597091A true JPS5597091A (en) 1980-07-23

Family

ID=11562669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP362579A Pending JPS5597091A (en) 1979-01-16 1979-01-16 Bistable nonvolatile memory circuit

Country Status (1)

Country Link
JP (1) JPS5597091A (en)

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