JPS559216A - Information processing circuit - Google Patents

Information processing circuit

Info

Publication number
JPS559216A
JPS559216A JP7991978A JP7991978A JPS559216A JP S559216 A JPS559216 A JP S559216A JP 7991978 A JP7991978 A JP 7991978A JP 7991978 A JP7991978 A JP 7991978A JP S559216 A JPS559216 A JP S559216A
Authority
JP
Japan
Prior art keywords
cpu
address
counters
ram
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7991978A
Other languages
Japanese (ja)
Other versions
JPS5927937B2 (en
Inventor
Osamu Akiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP53079919A priority Critical patent/JPS5927937B2/en
Publication of JPS559216A publication Critical patent/JPS559216A/en
Publication of JPS5927937B2 publication Critical patent/JPS5927937B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Microcomputers (AREA)

Abstract

PURPOSE: To alter the address, by increasing or decreasing the value of counter with the pulse from CPU, after reading in or writing out of data.
CONSTITUTION: The output port of CPU is connected to the input terminal of the counters L1 to L3 with preset functions, the output port of CPU is connected to the input terminal of RAM, and the output terminals of the counters L1 to L3 are connected to the address terminal of RAM. Further, the output terminals of RAM are connected to the input ports of CPU, the output signal from CPU presets the RAM address externally mounted to the counters L1 to L3, and when the continuous address data is accessed after readout or write-in of data, the pulse from CPU increases or decreases the value of the counters L1 to L3. Thus, the address can be changed.
COPYRIGHT: (C)1980,JPO&Japio
JP53079919A 1978-06-30 1978-06-30 information processing circuit Expired JPS5927937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53079919A JPS5927937B2 (en) 1978-06-30 1978-06-30 information processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53079919A JPS5927937B2 (en) 1978-06-30 1978-06-30 information processing circuit

Publications (2)

Publication Number Publication Date
JPS559216A true JPS559216A (en) 1980-01-23
JPS5927937B2 JPS5927937B2 (en) 1984-07-09

Family

ID=13703696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53079919A Expired JPS5927937B2 (en) 1978-06-30 1978-06-30 information processing circuit

Country Status (1)

Country Link
JP (1) JPS5927937B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197946A (en) * 1983-04-25 1984-11-09 Nec Corp Memory device
JPH0287254A (en) * 1988-09-22 1990-03-28 Nec Ic Microcomput Syst Ltd External memory access system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197946A (en) * 1983-04-25 1984-11-09 Nec Corp Memory device
JPH0287254A (en) * 1988-09-22 1990-03-28 Nec Ic Microcomput Syst Ltd External memory access system

Also Published As

Publication number Publication date
JPS5927937B2 (en) 1984-07-09

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