JPS5617424A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5617424A
JPS5617424A JP9458279A JP9458279A JPS5617424A JP S5617424 A JPS5617424 A JP S5617424A JP 9458279 A JP9458279 A JP 9458279A JP 9458279 A JP9458279 A JP 9458279A JP S5617424 A JPS5617424 A JP S5617424A
Authority
JP
Japan
Prior art keywords
cpu
ram
data transfer
data
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9458279A
Other languages
Japanese (ja)
Inventor
Isamu Shimoda
Minoru Yomoda
Teruya Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP9458279A priority Critical patent/JPS5617424A/en
Publication of JPS5617424A publication Critical patent/JPS5617424A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To prevent the number of data transfer lines from increasing not in proportion to the volume of data of a terminal, by providing a RAM memory between CPU and the terminal unit.
CONSTITUTION: CPU performs data transfer with RAM, which provides time- division data transfer with a circuit in a time other than the access time of CPU. While CPU is not in input-output operation with RAM, selector 4 selects an artificial address signal from counter 2 and data from RAM are selected, thereby exercising data transfer. CPU attains access to output RAM5 on an interface without access direct to the terminal and, after storing RAM5 temporarily with data to be output, outputs them from RAM5. Then, data are output by making use of the latch function that RAM possesses, so that a decoder on an address line can be eliminated
COPYRIGHT: (C)1981,JPO&Japio
JP9458279A 1979-07-23 1979-07-23 Data transfer system Pending JPS5617424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9458279A JPS5617424A (en) 1979-07-23 1979-07-23 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9458279A JPS5617424A (en) 1979-07-23 1979-07-23 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5617424A true JPS5617424A (en) 1981-02-19

Family

ID=14114261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9458279A Pending JPS5617424A (en) 1979-07-23 1979-07-23 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5617424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6347853A (en) * 1986-08-15 1988-02-29 Fujitsu Ltd Remote file accessing system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110238A (en) * 1974-02-05 1975-08-30
JPS50116143A (en) * 1974-02-26 1975-09-11
JPS5282039A (en) * 1975-12-29 1977-07-08 Fujitsu Ltd Display control

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110238A (en) * 1974-02-05 1975-08-30
JPS50116143A (en) * 1974-02-26 1975-09-11
JPS5282039A (en) * 1975-12-29 1977-07-08 Fujitsu Ltd Display control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6347853A (en) * 1986-08-15 1988-02-29 Fujitsu Ltd Remote file accessing system

Similar Documents

Publication Publication Date Title
JPS5617424A (en) Data transfer system
JPS5371537A (en) Information processor
JPS5685130A (en) Rom access circuit
JPS5437646A (en) Program loading system
JPS5619162A (en) Information protection system
JPS5356936A (en) Transfer control system
JPS5733472A (en) Memory access control system
JPS54151331A (en) Data processor
JPS5685176A (en) Picture data compressing device
JPS5572261A (en) Logic unit
JPS55159226A (en) Data input and output unit
JPS5384437A (en) Control system for test pattern generation
JPS55159257A (en) Debugging system
JPS55131829A (en) Transfer system of shared memory under communication control
JPS56101251A (en) Operation controller
JPS5665569A (en) Coding system for video signal
JPS5379329A (en) Test method of memory circuit
JPS5318354A (en) Time information output system
JPS5353930A (en) Input and output control system
JPS5517840A (en) Data transfer system
JPS5533224A (en) Sorting function integrated-circuit device
JPS551675A (en) Memory protect control system
JPS53112041A (en) Data processor
JPS5566041A (en) Extension system of storage capacity
JPS5640938A (en) Input/output control unit