JPS5692658A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5692658A
JPS5692658A JP16976079A JP16976079A JPS5692658A JP S5692658 A JPS5692658 A JP S5692658A JP 16976079 A JP16976079 A JP 16976079A JP 16976079 A JP16976079 A JP 16976079A JP S5692658 A JPS5692658 A JP S5692658A
Authority
JP
Japan
Prior art keywords
output
memory
address
limit value
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16976079A
Other languages
Japanese (ja)
Inventor
Tsutomu Sanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16976079A priority Critical patent/JPS5692658A/en
Publication of JPS5692658A publication Critical patent/JPS5692658A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make arbitrary a memory extension and to simplify the setting, by detecting the overflow from a DIP switch output designated with a final address and a comparator output of the upper limit value, in a memory system of a plurality of memory board constitutions.
CONSTITUTION: When a memory access signal is produced externally and information is given to the address line, it is input to comparators 3, 4, and when the address accessed is the lower limit value or more and within the upper limit value, the information is output to an AND gate 6. If the address exceeds the upper limit value, although the information is output from the comparator 4, output is always from the memory board handling the lower rank address space in constituting the system with a plurality of memory boards. The DIP switch 8 is provided, the logical product condition of the output and that of the comparator 4 is taken, and the output is taken as the address overflow signal. With the operation as mentioned above, the memory space is sectioned into the respective boards.
COPYRIGHT: (C)1981,JPO&Japio
JP16976079A 1979-12-26 1979-12-26 Memory unit Pending JPS5692658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16976079A JPS5692658A (en) 1979-12-26 1979-12-26 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16976079A JPS5692658A (en) 1979-12-26 1979-12-26 Memory unit

Publications (1)

Publication Number Publication Date
JPS5692658A true JPS5692658A (en) 1981-07-27

Family

ID=15892336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16976079A Pending JPS5692658A (en) 1979-12-26 1979-12-26 Memory unit

Country Status (1)

Country Link
JP (1) JPS5692658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245259A (en) * 1985-04-23 1986-10-31 Nec Corp Address control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245259A (en) * 1985-04-23 1986-10-31 Nec Corp Address control circuit

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