JPS5591157A - Mos dynamic memory - Google Patents

Mos dynamic memory

Info

Publication number
JPS5591157A
JPS5591157A JP16499378A JP16499378A JPS5591157A JP S5591157 A JPS5591157 A JP S5591157A JP 16499378 A JP16499378 A JP 16499378A JP 16499378 A JP16499378 A JP 16499378A JP S5591157 A JPS5591157 A JP S5591157A
Authority
JP
Japan
Prior art keywords
substrate
charge storage
memory
conductivity type
silicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16499378A
Other languages
Japanese (ja)
Inventor
Fumio Baba
Tomio Nakano
Seiji Emoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16499378A priority Critical patent/JPS5591157A/en
Publication of JPS5591157A publication Critical patent/JPS5591157A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain an IC memory having large operating allowance by employing a substrate having low impurity density and implanting the same conductivity type ion as the substrate to selecting FET portion excluding the lower portion of charge storage electrode. CONSTITUTION:A polycrystalline silicon layer serving as a cell charge storage electrode G2 is selectively formed on a substrate having low impurity density, and used as a mask to implant the same conductivity type ion as the substrate on a silicon layer. Thus, the charge storage portion incorporates a low threshold voltage, and the other portion incorporates a high threshold voltage to thereby write more charges than heretofore. In this case it is necessary to set the high (H) level of a word line WL higher than the power supply voltage when the threshold Vth of an FET transistor Q1 is high. This memory can prevent leakage of stored charge, provide long refreshing time and large operating allowance according to this configuration.
JP16499378A 1978-12-27 1978-12-27 Mos dynamic memory Pending JPS5591157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16499378A JPS5591157A (en) 1978-12-27 1978-12-27 Mos dynamic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16499378A JPS5591157A (en) 1978-12-27 1978-12-27 Mos dynamic memory

Publications (1)

Publication Number Publication Date
JPS5591157A true JPS5591157A (en) 1980-07-10

Family

ID=15803794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16499378A Pending JPS5591157A (en) 1978-12-27 1978-12-27 Mos dynamic memory

Country Status (1)

Country Link
JP (1) JPS5591157A (en)

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