JPS5589789A - Electronic watch - Google Patents

Electronic watch

Info

Publication number
JPS5589789A
JPS5589789A JP16373178A JP16373178A JPS5589789A JP S5589789 A JPS5589789 A JP S5589789A JP 16373178 A JP16373178 A JP 16373178A JP 16373178 A JP16373178 A JP 16373178A JP S5589789 A JPS5589789 A JP S5589789A
Authority
JP
Japan
Prior art keywords
frequency
frequency divider
output
gate
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16373178A
Other languages
Japanese (ja)
Inventor
Naoyuki Echigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP16373178A priority Critical patent/JPS5589789A/en
Publication of JPS5589789A publication Critical patent/JPS5589789A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain the desired reference period signal with high accuracy and to increase the massproduction, by counting the output of the frequency divider and changing the input frequency of the frequency divider at specified count value condition.
CONSTITUTION: The output frequency of the oscillator 1 is fed to the output terminal 6 and the n notation counter 7 as the reference period signal after being divided at the frequency divider 3 of the variable frequency divider circuit 2 via the gate 12. In this case, when the memory 4 and the content of the frequency divider 4 are detected for the coincidence 5, the frequency divider 3 is reset and the counter 7 counts one. Further, the coincidence of the contents of the counter 7 and the memory 8 are detected 9, and when the detection output of the circuits 5 and 9 are both obtained, the gate 12 if OFF and the gate 13 is ON, FF15 is triggered with the two pulses of the oscillation frequency, the output is given to the frequency divider 3 to invert the state of the gates 12 and 13. With the repetition of this operation, the frequency divided number of the circuit 2 is the value added with 1 to the content of the memory 4. Further, the content of the memories 4, 8 is determined with the oscillation frequency.
COPYRIGHT: (C)1980,JPO&Japio
JP16373178A 1978-12-28 1978-12-28 Electronic watch Pending JPS5589789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16373178A JPS5589789A (en) 1978-12-28 1978-12-28 Electronic watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16373178A JPS5589789A (en) 1978-12-28 1978-12-28 Electronic watch

Publications (1)

Publication Number Publication Date
JPS5589789A true JPS5589789A (en) 1980-07-07

Family

ID=15779586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16373178A Pending JPS5589789A (en) 1978-12-28 1978-12-28 Electronic watch

Country Status (1)

Country Link
JP (1) JPS5589789A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008180612A (en) * 2007-01-25 2008-08-07 Fujitsu Ltd Timer circuit and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008180612A (en) * 2007-01-25 2008-08-07 Fujitsu Ltd Timer circuit and program

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