JPS5682457A - Frequency detector - Google Patents

Frequency detector

Info

Publication number
JPS5682457A
JPS5682457A JP16048579A JP16048579A JPS5682457A JP S5682457 A JPS5682457 A JP S5682457A JP 16048579 A JP16048579 A JP 16048579A JP 16048579 A JP16048579 A JP 16048579A JP S5682457 A JPS5682457 A JP S5682457A
Authority
JP
Japan
Prior art keywords
pulse
counter
circuit
supplied
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16048579A
Other languages
Japanese (ja)
Inventor
Ryoichi Kurosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16048579A priority Critical patent/JPS5682457A/en
Publication of JPS5682457A publication Critical patent/JPS5682457A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE: To make possible the digital controlling of high stability by detecting the frequency of the pulse as digital value at every one pulse in controlling of an electric motor etc.
CONSTITUTION: The clock pulse from a generator 1 is divided down by a counter 2 and is supplied to a counter 5. When the pulse is inputted to the terminal 6, the pulse is supplied to a latch circuit 10 and a delay circuit 7, the delay output whereof starts a timer circuit 8. The output of the timer causes the counters 2, 5 to stop dividing and counting operations. A level change in the timer output causes the counters to start dividing and counting operations. The count value of the counter 5 becomes the address input to a memory circuit 3, and the corresponding data of the circuit 3 are applied to the counter 2, whereby the frequency dividing ratio thereof is determined. When the next input pulse is supplied, the count value is latched, and the digital value proportional to the frequency is obtained instantaneously.
COPYRIGHT: (C)1981,JPO&Japio
JP16048579A 1979-12-11 1979-12-11 Frequency detector Pending JPS5682457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16048579A JPS5682457A (en) 1979-12-11 1979-12-11 Frequency detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16048579A JPS5682457A (en) 1979-12-11 1979-12-11 Frequency detector

Publications (1)

Publication Number Publication Date
JPS5682457A true JPS5682457A (en) 1981-07-06

Family

ID=15715953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16048579A Pending JPS5682457A (en) 1979-12-11 1979-12-11 Frequency detector

Country Status (1)

Country Link
JP (1) JPS5682457A (en)

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