JP2008180612A - Timer circuit and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timer circuit and a program for a portable device or the like, which can prevent the accumulation of errors even if a low frequency (32KHz) quartz oscillator is used or timing is carried out for a long time. <P>SOLUTION: The timer circuit includes a first counter that counts outputs from the low frequency quartz oscillator to generate an output substantially every 1 millisecond, and a second counter that counts the outputs from the first counter to generate an output every m millisecond, wherein the output from the second counter is supplied to a processor. The timer circuit further includes an electronic switch for switching the first counter so that it counts at either one of the count capacities of "32" and "33", and an adjustment determining circuit for determining whether the count value of the second counter is equal to one of lots of dispersed values previously set, and generates an instruction on switching. The count value of the first counter is switched in compliance with the instruction on switching, and thereby, a signal of which errors from a clock circuit have been corrected is output from the second counter. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a timer circuit and a program for a portable device.

  Various portable devices such as mobile phones are provided with timer circuits for various time monitoring, and it is desired to maintain accurate time and reduce power consumption. Note that the timer circuit may be provided as a circuit (hardware) separate from the processing device (CPU and memory). However, a specific area of the memory is used as the timer area, and the contents read from the timer area are shared. There may be a case where it is realized by a method of counting by an arithmetic circuit (processing device) and storing in the timer area.

  FIG. 5 is a diagram showing a configuration of the conventional example 1, which is an example of a timer circuit used in a mobile phone. In the figure, reference numeral 80 denotes a crystal oscillator, which often has an oscillation frequency of 32.768 KHz in order to reduce power consumption. Reference numeral 81 is a 10 msec counter, 82 is a CPU that performs control processing of the mobile phone, and 83 is a clock circuit that generates a clock display or alarm output to the CPU 82 at regular intervals.

  In the configuration of FIG. 5, the output of the crystal oscillator 80 is counted by the counter 81, and when the signal generated inside 10 msec is counted by the set value (n) given from the CPU 82, an output is generated to the CPU 82. The clock circuit 83 generates an interrupt signal every 1 second or 1 minute.

  To configure the 1 msec timer by counting the 32.768 KHz output of the crystal oscillator, the count is 33 times. However, an error of 0.7% occurs in the output of the timer. For example, if the counter 81 is used as a timer for 1 second (1000 msec), the error of 0.7% reaches 7 msec. If the time of 1 minute is counted, the error becomes 420 msec. The error with the timer using the clock circuit becomes large.

  Specifically, in the example of executing an application for playing back a moving image on a mobile phone, various inconveniences such as a shift between the moving image and sound occur.

  Note that the counter 81 in FIG. 5 is used as a 10 msec timer in order to reduce the error, and the lapse of 10 msec can be measured by counting the clock of 32.768 KHz 327 times, but still 0.02 msec. Therefore, it is necessary to perform a process for absorbing the error in the process for each function using the timer.

  In the case of a timer that requires accuracy, it is configured with a counter circuit using a high-frequency crystal oscillator of 8 to 10 MHz. However, since the current consumption increases when the frequency is high, a battery such as a mobile phone is used. There was a problem that the device could not be used at all times. Even if a high-frequency oscillator is used, a slight error occurs, and the error accumulates, resulting in a large error after a long time. As a countermeasure, there has been proposed a method for improving the timing accuracy by changing the preset data of the counter constituting the timer by a periodic operation to make the count value of the timer variable (see Patent Document 1).

FIG. 6 shows the configuration of Conventional Example 2 and includes the configuration of Patent Document 1 described above. In the figure, 80, 82 and 83 are the same as those in FIG. 5, 80 is a crystal oscillator of 32 KHz (exactly 32.768 KHz), 82 is a CPU, and 83 is a clock circuit. 85 is an 8 MHz crystal oscillator, 86 is an 8-bit binary counter that generates 1 msec output, and 87 is a binary counter preset when a carry signal (carry signal from the most significant digit) is generated from the binary counter. A preset data switching circuit for generating variable binary data. A configuration comprising 85 to 87 of this circuit is proposed by the above-mentioned patent document 1, and the preset data switching circuit 87 counts a carry signal from the binary counter 86 and counts a fixed number to an auxiliary counter 870. The binary counter 86 includes a preset data creation circuit 871 that is preset every cycle. When a carry signal is generated from the binary counter 86, the auxiliary counter 870 of the preset data switching circuit 87 counts, and the carry signal becomes an update start signal and the data set in the preset data creating circuit 871 and the count of the auxiliary counter 870 are counted. The value (partial bits) is set as a preset value in the binary counter 86. As a result, the update period of the binary counter 86 changes the preset value, thereby improving the timing accuracy.
JP 54-102939 A

  Even in the configuration of the conventional example 2 (FIG. 6), an error occurs due to the difference between the oscillation accuracy of the clock circuit 83 and the crystal oscillator 80 operating at 32 KHz and the oscillation accuracy of the 8 MHz crystal oscillator 85 and the counter 86. I cannot solve the problem. Further, it is unavoidable to accumulate errors due to the difference in the degree of influence between the crystal oscillator for clock 80 and the high-frequency crystal oscillator 85 for counter due to temperature and voltage fluctuations. For this reason, it is necessary to take measures such as correcting the error due to accuracy, temperature and voltage fluctuations for each application.

  Further, since the configuration of Conventional Example 2 uses a high-frequency (8 MHz) crystal oscillator, it consumes a lot of power and has a problem in application to a portable device such as a cellular phone using a battery.

  An object of the present invention is to provide a timer circuit and a program for a portable device that can prevent accumulation of errors regardless of whether a low-frequency (32 KHz) crystal oscillator is used or time is measured for a long time.

  FIG. 1 is a diagram showing a principle configuration of the present invention. In the figure, 1 is a low-frequency (32.768 KHz) crystal oscillator, 2 is a clock from the crystal oscillator 1 and counts only one of the two capacities (numerical values) of “32” or “33”. A first counter that generates an output approximately every 1 millisecond; 20 is a switching circuit that generates the first counter 2 by switching between the two numbers; and 3 is a first counter. The signal generated from 2 is counted almost every millisecond, and “m” (m = 125 (milliseconds), 250 (milliseconds), 375 (milliseconds), 500 (milliseconds), etc. A second counter that generates an output every time, and 30 is a number of distributed settings until the count value of the second counter 3 reaches the value of “m” for error adjustment. When a match with the value is detected, the switching circuit 20 is switched. An adjustment determination circuit to be instructed, 30a is a set value holding unit, 4 is a processing device such as a mobile phone to which the output of the second counter 3 is input, and 5 is driven by the crystal oscillator 1 to This is a clock circuit that generates an interrupt signal to the processing device 4 at a constant cycle such as every second or every minute.

  The low-frequency (32.768 KHz) clock signal output from the crystal oscillator 1 is counted by the first counter 2, and when the count number set corresponding to the switching state at that time is reached in the switching circuit 20, the output is output. Generated and supplied to the second counter 3. The count capacity of the first counter 2 is switched to a capacity of “32” or “33” by the output of the switching circuit 20 that is switched by the determination output from the adjustment determination circuit 30. In this example, the count capacity is normally “33”, and the switching circuit 20 is switched to the count capacity of “32” by the determination output from the adjustment determination circuit 30. While the count value of the second counter 3 is always input to the adjustment discriminating circuit 30, a large number of dispersed values among the values generated between 1 and m of the count value of the second counter 3 are set. If any one of the set value holding units 30a matches the count value of the second counter 3, a switching signal is generated each time a match is detected, and the switching circuit 20 counts the count number “32”. It is switched as follows. The count value held in the set value holding unit 30a is “5”, “9”, “14”, “18”, “22”, “26”, “30”, “35” when m = 125. , “39”, “44”, “48”, “52”,..., “120”, “125”, and when m = 250, “5”, “9”, “14”,. …, “120”, “125”, “130”, “134”, “139”..., “250”, and when m = 375, “5”, “9”,. The numerical values 125, 130, 134,..., “250”, “255”, “259”,.

  As a result, when m = 125, the second counter 3 notifies the switching signal at the time when each of the count values from 1 to 125 is counted, and the switching circuit 20 receives the switching signal. Every time the first counter 2 is switched to a count capacity of “32”.

  If the time error due to the frequency error of the crystal oscillator 1 is a maximum monthly difference of ± 15 seconds, the error per minute is a maximum of ± 347.2 microseconds. In order to adjust this error, in order to measure one minute with a clock circuit, a place where 32768 counts per second is normally performed once every few seconds, +1 and 32769 counts, or conversely −1 and 32767 counts. In general, it is provided with a function of adjusting. Accordingly, when measuring 1 ms, the frequency error of the 32.768 KHz crystal oscillator is adjusted by changing the count of 32 times to 33 times or changing the count of 33 times to 32 times. However, it is also possible to perform correct clock counting by absorbing clock errors.

  The output of the second counter 3 is input directly to the processing device 4 or counted by a counter (not shown) and input to the processing device 4 every second or every minute. Based on the clock, it is possible to reduce the time difference with respect to the interrupt signal supplied from the clock circuit 5 to the processing device 4 such as a CPU at regular intervals of 1 second, 1 minute, or the like. The second counter (millisecond output counter) 3 has a count capacity of m (milliseconds). By counting the output with a counter (not shown), for example, a 1 second counter is configured. be able to. In this case, the time point when the first counter 2 is switched to “32” is not only +125 but also +250, +375,.

  The second counter 3 generates an output every time “m” is counted, and for example, 10 seconds each time the output is counted by another counter (not shown) (or counted by a counting operation in the processing device 4). Alternatively, an output is generated in the processing device 4 at a constant time period of 1 minute, but errors accumulate in the second counter 3 at a long time period. When it is necessary to adjust an error that occurs in such a long time period, an instruction signal 4a is output from the processing device 4 to the second counter 3 at regular time intervals. Receiving this, the second counter 3 sets its count capacity to +1 (126) or -1 (124) instead of "125". Thereby, the output generated from the second counter 3 can be corrected within a certain long time period.

  By switching the count capacity of the first counter in units of distributed milliseconds according to the present invention, it is possible to measure time with an error of 1 ms – 1/32768 × 32 ms = 0.0234 ms for a maximum of 1 millisecond and continuous measurement. It is possible to prevent errors from accumulating even when measuring for a long time. Further, accumulation of errors can be prevented by adding or subtracting the count capacity of the second counter 3 by 1 every certain period of time (such as 10 seconds or 1 minute).

  The configuration of an embodiment in which the present invention uses a computer (including a CPU and a storage device) constituting a control device for a portable device such as a cellular phone will be described. FIG. 2 shows a configuration of an embodiment using specific areas of the CPU and the storage device. In the figure, 6 is a CPU including a program memory, 60 is a crystal oscillator, 7 is a memory including a plurality of areas (registers) for timers, 70 to 72 are areas provided in the memory 7, and 70 is An area of a 1 millisecond counter (corresponding to the first counter 2 in FIG. 1) for counting the set numerical value (“32” or “33”) of the output of the crystal oscillator (32.768 KHz), 71 is 1 An area of an m millisecond counter (corresponding to the second counter 3 in FIG. 1) that counts up each time it detects that the millisecond counter 70 has counted a set numerical value (“32” or “33”); 72 is a period n for adjusting the value of the m millisecond counter 71 to +1 or −1 every period of m milliseconds × n (for example, when n = 80, a period of 80 × 125 milliseconds = 10 seconds) For counting) The error adjustment counter area 73 has a large number of distributed count values (m millisecond counter values) for generating an instruction to change the count value of the counter area 70 to “32” instead of the usual “33”. This is the area of the set part.

  Note that the setting unit 73 includes “5”, “9”, “14” when m = 125 as the count value of the m millisecond counter 71 for setting the 1 millisecond counter 70 to “32 times”. , “18”, “22”, “26”,..., “125” are set. In addition, m of the m millisecond counter 71 can be set not only to 125 but also to m = 250, 375, 500, 725,... In addition to “9”,..., “125”, each value such as “125 + 5 = 129”, “125 + 9 = 134”,... “125 + 125 = 250”,. Can be set.

  3 and 4 are flowcharts (part 1) and (part 2) of the embodiment. This flowchart is an example in which the m millisecond counter 71 shown in FIG. 2 is used as a 125 millisecond counter, and will be described as a 125 millisecond counter 71. In this case, as described above, “5”, “9”, “14”,..., “125”, which are a plurality of dispersed values not exceeding 125 as described above, are set.

  When the operation is started, the misadjustment counter (72 in FIG. 2) is set to 0 (S1 in FIG. 3), and the number of 1 millisecond counters (70 in FIG. 2) (count capacity) is set to 33 ( The S2) and 125 millisecond counter (71 in FIG. 2) is set to 0 (S3 in FIG. 3). Next, it is determined whether the number of counters of the 1 millisecond counter 70 is “32” (S4 in FIG. 3). This determination is executed every 1/32768 seconds, and it is determined whether the count value set for the 1 millisecond counter 70 at that time is “32 times” or “33 times” (FIG. 3). S4). This setting is performed in step S11 or S12, which will be described later, and the 1-millisecond counter 70 is operated to count 32 times (S5 in FIG. 3) or 33 times (S6).

  Thereafter, it is determined whether or not the 1-millisecond counter 70 has counted up to the set number of times determined above ("32" or "33") (S7 in FIG. 3). If not counted up, the process returns to step S4. When the count is counted up, the 125 millisecond counter 71 is counted up (S8). Next, it is determined whether there is a counter adjustment (S9 in FIG. 3). In this counter adjustment, it is determined whether or not it is necessary to adjust an error that occurs with respect to a predetermined time length preset with respect to the 125 millisecond counter 71. It depends on the presence or absence of instructions from 6). If there is an adjustment, an area in which a numerical value of m in 125 milliseconds × m is set (for example, when m = 80, 125 milliseconds × 80 = adjustment once every 10 seconds) is provided, and no adjustment is made. If this is the case, keep the numbers from being set. If it is determined that there is an error adjustment, the process proceeds to the process of FIG. 4 (described later).

  If the 125 millisecond counter is not adjusted, the current 125 millisecond counter value corresponds to one of the numerical values of the setting unit (73 in FIG. 2) to be corrected by 1 millisecond. It is determined whether it is present (S10 in FIG. 3). If it matches one of the numerical values in the setting section, the 1 millisecond counter 70 is set to 32 times (S11 in FIG. 3), and if not, it is set to 33 times (S12). Thereafter, it is determined whether or not the 125 millisecond counter has reached 125 (S13 in FIG. 3). If it has been reached, 0 is set in the 125 millisecond counter (S14 in the same), and it is determined whether or not there is counter adjustment (FIG. 3). S15). This determination is the same as in step S9, and when there is an adjustment, the error adjustment counter (72 in FIG. 2) is counted up (S16 in FIG. 3), and when there is no counter adjustment and the error adjustment is counted up. After that, it is determined whether the time is up (S17). In this case, when the time to be measured such as 1 second or 1 minute is determined in advance, it is determined whether the determined time has been reached. If not reached, the process returns to step S4, and if reached, time-up processing is executed (S18). The time-up process is to execute a process (interrupt, output, etc.) determined to be executed when a predetermined time is reached.

  FIG. 4 is a flowchart in the case of counter adjustment, and is executed when it is determined as YES in step S9 of FIG. First, it is determined whether the error adjustment counter is equal to the set value (S19 in FIG. 4). For example, when the set value m = 80, it is determined whether the error adjustment counter (72 in FIG. 2) is “80”, and when it is “80”, it is determined whether it is “+1 count” or “−1 count”. (S20 in FIG. 4). In this case, whether “+1” or “−1” is set in advance according to the characteristics of the timer circuit, and is determined by determining the setting. When the +1 count is executed, it is determined whether the 125 millisecond counter 71 has become “125” (S21 in FIG. 4). If not 125, the process proceeds to step S10 in FIG. Sets the 1 millisecond counter 70 to "33" count (S22), and proceeds to step S25.

  When it is determined that the count is “−1” in step S20 and “−1” is executed, it is determined whether the 125 millisecond counter 71 has become “124” (S23 in FIG. 4), and is determined to be “124”. The 1-millisecond counter 70 is set to “32” count (S24), then the error adjustment counter (72 in FIG. 2) is set to 0 (S25), and the process proceeds to step S13 in FIG. If it is determined in step S19 that the error adjustment counter is not the set value, or if it is determined in step S23 that the 125 millisecond counter 71 is not "124", the process proceeds to step S10 in FIG.

  If the time error due to the frequency error of the crystal oscillator is a maximum monthly difference of ± 15 seconds, the error per minute is a maximum of ± 347 μs. In order to adjust this error, in order to measure one minute by the time measuring circuit, the normal count of 32768 is performed once every few seconds, and is incremented once every several seconds to +32768, or vice versa. The function of counting and adjusting is generally performed. Correspondingly, when counting 1 millisecond, the frequency error of the 32.768 KHz crystal oscillator is changed by counting the number of times 32 times to 33 times or changing the number of times 33 times to 32 times. It is possible to correct the clock and correct the clock by absorbing the clock error.

  (Supplementary Note 1) A first counter that counts the output of a low-frequency crystal oscillator and generates an output every 1 millisecond, and counts a predetermined number (m) of the output of the first counter to m millimeter In a second counter that generates an output per second and a timer circuit that supplies the output of the second counter to the processing device, the first counter is one of two count capacities of “32” or “33”. A switching circuit that switches to count at the same time, and the switching circuit that determines if the count value of the second counter matches a plurality of dispersed preset values that are less than or equal to the count capacity (m) of the second counter. And an adjustment discriminating circuit for generating a switching instruction, and an error from the clock circuit is corrected by switching the count capacity of the first counter according to the switching instruction from the adjustment discriminating circuit. A timer circuit for a portable device, wherein the output from said second counter to issue.

  (Supplementary note 2) In Supplementary note 1, the processing device generates an instruction signal to increase or decrease the count capacity of the second counter by 1 every predetermined time length set in advance, and the second counter A timer circuit for a portable device, wherein the count capacity is changed by a signal.

  (Supplementary Note 3) In Supplementary Note 1, another counter that counts the output of the second counter by a preset number of times is provided, and the output of the other counter is supplied to the processing device. A timer circuit for a portable device, which generates an instruction to adjust the count value of the second counter at regular intervals based on the output of the counter.

  (Supplementary Note 4) A computer that controls the portable device is configured to count a value in a 1 millisecond counter area in the memory in response to generation of an output of a low-frequency crystal oscillator, and the 1 millisecond counter It is determined which of the two count capacities “32” or “33” is set, and whether the counted-up value has reached the determined count capacity is determined. A means for counting up the numerical value in the second counter area, and when counting up the numerical value in the m millisecond counter area, it is determined whether or not it matches a number of dispersed values preset in the setting area in the memory. Then, the count capacity of the 1 millisecond counter area is set to “32”, and if it does not match, it is set to “33” and the numerical value of the m millisecond counter area is counted. Means for determining has been reached on the amount, the the value of m millisecond counter area reaches the count capacity, program characterized thereby and means for performing a time-up process, to function.

  (Supplementary note 5) In the supplementary note 4, when the means for determining whether the numerical value in the m millisecond counter area has reached the count capacity is detected, the numerical value in the error adjustment counter area provided in the memory is detected. A function for counting up, and a means for counting up the numerical value of the m millisecond counter area, and further detecting that the numerical value of the error adjustment counter area has reached a preset value; A program for increasing or decreasing a value in a counter area by 1 to function as means for setting a value in an error adjustment counter area to 0.

It is a figure which shows the principle structure of this invention. It is a figure which shows the structure of the Example which uses the specific area | region of CPU and a memory | storage device. It is a figure which shows the flowchart (the 1) of an Example. It is a figure which shows the flowchart (the 2) of an Example. It is a figure which shows the structure of the prior art example 1. FIG. It is a figure which shows the structure of the prior art example 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Low frequency (32.768 KHz) crystal oscillator 2 1st counter 20 Switching circuit 3 2nd counter 30 Adjustment discrimination circuit 30a Setting value holding | maintenance part 4 Processing apparatus 5 Clock circuit

Claims (3)

A first counter that counts the output of a low-frequency crystal oscillator and generates an output every 1 millisecond, and outputs every m milliseconds by counting a predetermined number (m) of the output of the first counter And a timer circuit for supplying the output of the second counter to the processing device,
The first counter is a switching circuit for switching to count one of the two count capacities of “32” or “33”;
An adjustment discriminating circuit for discriminating whether or not the count value of the second counter coincides with a plurality of dispersed preset values less than or equal to the count capacity (m) of the second counter and generating a switching instruction to the switching circuit And
A timer for a portable device, wherein a signal corrected for an error with respect to a clock circuit is output from the second counter by switching a count capacity of the first counter according to a switching instruction from the adjustment determination circuit. circuit. In claim 1,
The processing device generates an instruction signal for increasing or decreasing the count capacity of the second counter by 1 every predetermined time length,
The timer circuit for a portable device, wherein the second counter changes a count capacity according to the instruction signal. A computer that controls the mobile device,
Means for counting up the value of the 1 millisecond counter area in the memory in response to the generation of the output of the low frequency crystal oscillator;
When determining whether the 1 millisecond counter is set to two count capacities of “32” or “33”, determining whether the counted up value has reached the determined count capacities, and reaching Means for counting up the numerical value of the m millisecond counter area in the memory;
When the numerical value in the m millisecond counter area is counted up, it is determined whether or not it matches a large number of dispersed values preset in the setting area in the memory. Means for setting whether the numerical value in the m millisecond counter area has reached the count capacity,
Means for performing time-up processing when the numerical value of the m millisecond counter area reaches the count capacity;
A program characterized by making it function.

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