JP2006053008A - Timepiece and timepiece error adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timepiece and a timepiece error adjustment method for efficiently performing timepiece setting with high accuracy by utilizing record data used by a user himself/herself for adjusting the gaining or losing of time, and dispensing with special components and dispensing with particular correction/adjustment even at factory shipment. <P>SOLUTION: This timepiece is equipped with a time counter 4 for measuring time; an operation means for operating timepiece setting; a means for detecting whether a timepiece has been set forward or set back in cases where the user performs time change; a means for performing adjustment to accelerate or delay clocking motion of the time counter according to detected matter; and a means for changing the degree of adjustment on the accelerated amount or delayed amount of a counter value on the time counter according to the size of a numerical value of an accumulation result, by accumulating operation details on whether an accelerating operation is performed or a delaying operation is performed for each time from the first time onward, when thereafter performing timepiece setting from the second time onward. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a timepiece and a timepiece error adjustment method, and in particular, in a timepiece used in an electronic device, when a user performs an operation of correcting time advance or delay, the content or time correction data is used. In addition, the present invention relates to a timepiece and a timepiece error adjustment method capable of efficiently correcting the time delay error characteristics of individual timepieces.

  2. Description of the Related Art Conventionally, in an electronic device, a clock that counts and displays time by controlling a clock function unit (hereinafter referred to as a time counter) and a display driving unit with a CPU is used. In order to maintain an accurate time on the watch, a correction value for the time lag (error) is obtained by comparing each watch with a highly accurate reference time in the inspection process before shipment at the manufacturing factory. Measures such as setting were taken, or correction adjustment was not performed at all, and the user manually adjusted the clock as needed after entering the market.

  The main cause of the advance or delay of the clock occurs because the oscillation frequency deviates from the ideal frequency. The main cause of this deviation is considered to be variation in characteristics of components constituting the vibrator and the oscillation circuit, variation in driving capability of the oscillation driver, and fluctuation due to voltage and temperature changes for all of them.

For example, in Patent Document 1, a crystal resonator used as an oscillator of a real-time clock (RTC) has temperature characteristics. In order to correct a time error caused by this temperature change, a power source of an apparatus equipped with an RTC is disclosed. When the apparatus is turned on, the time error is corrected with the first correction value based on the temperature inside the apparatus, and the time error is corrected with the second correction value based on the outside temperature of the apparatus while the apparatus is turned off. It is described.
JP 2002-365383 A

  By the way, when adjusting the timepiece in the inspection process, it is necessary to measure the accuracy of the timepiece with a dedicated measuring device, and the inspection time increases because each piece is inspected, which is disadvantageous in terms of cost. It was.

  Further, even if adjustment is performed in the inspection process and the deviation is corrected, there is a possibility that the clock accuracy may change due to the difference in the surrounding environment actually used and the fluctuation of the part characteristics due to the change with time.

  On the other hand, the method of determining the RTC correction value by the temperature sensor as in Patent Document 1 requires a special part such as a sensor for the correction, which is disadvantageous in reducing the cost.

  Therefore, in view of the above problems, the present invention does not require any special parts such as sensors, and the user corrects the time advance or delay by himself without performing any correction adjustment even when shipped from the factory. It is an object of the present invention to provide a timepiece and a timepiece error adjustment method capable of efficiently and accurately performing time setting using the correction contents or the correction time data at the time.

  A timepiece according to the present invention includes a time counter for measuring time, an operation means for operating time adjustment, and a means for detecting whether the change has advanced or delayed when the user changes the time. In accordance with the detection contents, the time counter operation is adjusted to speed up or delay, and when the second time adjustment operation is performed thereafter, the advance operation is performed every time from the first time. Means for accumulating operation contents indicating whether or not a delay operation has been performed, and changing the degree of adjustment of the advance amount or delay amount of the counter value of the time counter according to the value of the accumulated result. It is a thing.

  Further, the clock error adjustment method according to the present invention is a clock error adjustment method when the user performs an operation for correcting the advance or delay of the time, and the change is made when the user changes the time. Detecting whether the time has been advanced or delayed, and adjusting the speeding up or delaying of the time counter according to the detected contents, and then performing the second and subsequent time adjustment operations Each time from the first time, the operation content indicating whether the advance operation or the delay operation was performed is accumulated, and the advance amount or delay amount of the counter value of the time counter is determined according to the magnitude of the numerical value of the accumulation result. Change the degree of adjustment.

  According to the clocks of the invention and the error adjustment method thereof, when the user corrects the time advance or delay by manipulating the time advance or delay, in the first clock adjustment, when the time is advanced, the speed of the time measuring operation is increased. When the speed is increased and delayed, the timing operation is automatically adjusted to be delayed. In the second and subsequent clock adjustments, the degree of adjustment of the advance amount or delay amount is automatically changed according to the past accumulated result of the advance or delay correction operation. That is, when the user changes the clock due to the advance or delay of the clock, it detects whether the change has advanced or delayed the time, and the time counter measures the time according to the detected content. Adjust to speed up or slow down. After the adjustment, if there is an operation to change the time, the watch adjustment contents (advanced or delayed) are accumulated, and the counter value of the time counter is adjusted according to the magnitude of the accumulated result of the adjustment contents. Change how fast or slow.

  Furthermore, the timepiece according to the present invention includes a time counter for measuring time, an operation means for operating time adjustment, a means for storing the time immediately after the previous time adjustment, and a timekeeping time immediately before the current time adjustment. Means for storing, means for storing the time immediately after the time adjustment, means for calculating the advance amount or delay amount per unit time from these three time values, and the advance amount per unit time or Means for adjusting the counter value of the time counter using a delay amount.

  The clock error adjustment method according to the present invention is a clock error adjustment method when the user performs an operation to correct time advance or delay, and stores the time immediately after the previous time adjustment. This time, memorize the time just before the time adjustment, memorize the time immediately after the time adjustment this time, calculate the amount of advance or delay per unit time from these three time values, this unit time The counter value of the time counter is adjusted using the winning advance amount or the delay amount.

  According to the timepieces and their error adjustment methods of these inventions, the correct time when the clock was adjusted last time, the time measured including the error immediately before the current clock was adjusted, and the correct time immediately after the current clock was adjusted An advance amount or delay amount per unit time is calculated from the three values, and an error based on a clock error characteristic of the timepiece can be corrected by adjusting a counter value of the time counter using the calculation result.

 Embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the timepiece according to the first embodiment of the present invention.

  In FIG. 1, a timepiece includes a CPU 1, an input / output means (hereinafter referred to as I / O) 2, a bus line 3, a time counter 4, a nonvolatile memory 5, an LCD controller 6, a driver 7, a liquid crystal ( Hereinafter, LCD) 8 is provided.

  The CPU 1 controls each part of the timepiece based on the control program. The I / O 2 is connected to the CPU 1 and includes an operation unit such as a switch for delaying the time of the clock. The time counter 4 generates time data under the control of the CPU 1.

  The nonvolatile memory 5 is configured by an EEPROM, a flash memory, or the like. The nonvolatile memory 5 is connected to the bus line 3, and when the CPU 1 detects the user's time change operation by the I / O 2, when the second time adjustment operation is performed, the non-volatile memory 5 starts from the first time. Each has a function of storing an operation content indicating whether an advance operation or a delay operation is performed, performing an operation of accumulating the operation content, and storing the accumulated result. The LCD controller 6 controls the LCD driver 7 under the control of the CPU 1.

  The CPU 1 receives a switch operation signal from the I / O 2 and supplies necessary data to the time counter 4, the flash memory 5, and the LCD controller 6 through the bus line 3, and supplies control signals for controlling them. To do.

  When the user changes the time, the CPU 1 detects whether the change has advanced or delayed the time, and adjusts to speed up or delay the time counter according to the detected content. When the time adjustment operation after the second time is performed, the operation contents of whether the advance operation or the delay operation was performed is accumulated every time from the first time. And a function of changing the degree of adjustment of the advance amount or the delay amount of the counter value of the time counter according to the magnitude.

  Next, the operation of FIG. 1 will be described with reference to FIG. FIG. 2 is a flowchart showing the operation at the time adjustment in the timepiece of FIG. In FIG. 2, (a) shows the operation at the first time adjustment, and (b) shows the operation at the second and subsequent time adjustment.

  When the user performs a time adjustment operation, the CPU 1 detects this operation and enters the time adjustment process (time change mode) of the clock as shown in FIG. 2A (step S1). (Step S2). If the time adjustment is advanced by the time adjustment operation, the time counter 4 is accelerated, and if the time adjustment is delayed, the time counter 4 is operated. Adjustment to delay is performed (step S3).

  Thereafter, as shown in FIG. 2 (b), when the time adjustment operation is performed for the second time and thereafter, the operation contents indicating whether the advance operation or the delay operation has been performed is accumulated every time from the first time (step S5). If the time adjustment is advanced, 1 is added to the previous accumulated result, and 1 is subtracted if it is delayed. For example, when the time adjustment is advanced three times, the accumulated result = 1 + 1 + 1 = 3, and when the first time adjustment is advanced and delayed for the second time, the accumulated result = 1-1 = 0.

  Then, the degree of adjustment of the advance amount or delay amount of the counter value of the time counter 4 is changed according to the numerical value of the accumulated result (step S6).

  Next, a specific example of a method for speeding up or delaying the time counting operation of the time counter 4 will be described.

Example 1. Correction of the count value by the time counter 4 (the correction period is constant and the correction amount is changed)
For example, the CPU 1 reads out a 1/10 second count value from a 1/10 second counter included in the time counter 4 every arbitrary fixed time, such as every hour, and performs addition / subtraction correction on the count value. Write to the time counter 4 to update the time counter value. The time counter 4 is a multi-stage counter (such as a 1/10 second counter, a second counter, a minute counter, an hour counter, a day counter, etc.) that performs a frequency division operation so as to sequentially carry up 32.768 kHz of the crystal resonator. ) Is a correction target, but the counter to be corrected may be changed according to the correction accuracy.

<Operation example>
・ To speed up the time: Increase the counter value. The value to be added is larger as the accumulated time alignment result is larger.

Cumulative result Counter value Corrected counter value
+1 0.5 → 0.6 (seconds)
+2 0.5 → 0.7 (seconds)
+3 0.5 → 0.8 (seconds)
・ Delay time: Decrease the counter value. The decreasing value is subtracted more as the time alignment cumulative result becomes negative.

Cumulative result Counter value Corrected counter value
-1 0.5 → 0.4 (seconds)
-2 0.5 → 0.3 (seconds)
-3 0.5 → 0.2 (seconds)
Example 2. Correction of the count value by the CPU 1 (the correction amount is fixed and the correction cycle is changed) The correction value to be corrected by one counter correction operation is an arbitrary fixed value, and is added or changed depending on whether the accumulated result is positive or negative Perform subtraction operation.

  The procedure in which the CPU 1 reads and corrects the counter value of, for example, the 1/10 second counter of the time counter 4 and updates the counter value is the same as that in the first example.

  Then, the greater the absolute value of the accumulated result, the shorter the cycle for performing the counter correction. As a result, when the absolute value of the cumulative result is large, the correction cycle is shortened, so the value counted within a certain time can be increased and the correction amount within the certain time can be increased, and when the absolute value of the cumulative result is small, Since the correction cycle becomes longer, the value counted within a certain time is reduced and the correction amount within the certain time can be reduced.

Example 3 Correction of the count value by the time counter 4 The CPU 1 sets the time counter 4 to change the count-up operation according to the contents of the accumulated result.

  Example) The count-up operation of the 1/10 second counter is changed according to the accumulated result, for example, once an hour.

  It is determined that the greater the cumulative result is, the greater the degree of time delay is, and the count-up is further accelerated. That is, the count-up operation amount is increased. Conversely, it is determined that the greater the cumulative result is, the greater the degree of advance of the hour hand, and the count-up is delayed. That is, the count-up operation amount is reduced.

  The frequency of applying this correction and the control of the count-up operation can be arbitrarily changed.

Cumulative result 1/10 second counter operation
+1 0.0 → 0.2 → 0.3 → 0.4 → 0.5…
+2 0.0 → 0.4 → 0.5 → 0.6 → 0.7…
+3 0.0 → 0.6 → 0.7 → 0.8 → 0.9…
0 0.0 → 0.1 → 0.2 → 0.3 → 0.4…
-1 0.0 → 0.0 → 0.1 → 0.2 → 0.3 ...
-2 0.0 → 0.0 → 0.0 → 0.1 → 0.2…
-3 0.0 → 0.0 → 0.0 → 0.0 → 0.1…
According to the first embodiment described above, since the data of the time counter is corrected based on the time adjustment result of the advance / delay performed by the user, it is not necessary to adjust the time correction at the time of shipment, and the oscillation circuit Since it is not necessary to increase the accuracy of the components constituting the time counter, the time counter can be corrected at low cost.

  In addition, it is possible to flexibly cope with changes in the oscillation characteristics over time and changes in the usage environment.

  The configuration of the timepiece according to the second embodiment of the present invention is the same as that shown in FIG.

  FIG. 3 is a block diagram showing the configuration of the time counter (reference numeral 4 in FIG. 1) in the timepiece according to the second embodiment of the present invention, and FIG. 4 is a flowchart for explaining the operation of the time counter 4.

  In FIG. 3, the time counter 4 receives a signal having an oscillation frequency of 32.768 kHz from a crystal resonator (not shown), divides the signal into 1/512 and generates a 64 kHz signal, A second clock generation circuit 12 with a correction function for inputting a 64 kHz signal from the frequency divider circuit 11, various correction control signals from the CPU 1 and a one-minute clock, and generating a one-second clock (abbreviated as 1 s clock); Second counter 13 that inputs 1s clock and generates 1 minute clock (abbreviated as 1m clock), minute counter 14 that inputs 1m clock and generates 1 hour clock (abbreviated as 1h clock), and 1h clock are input And a day counter 15 for generating a 1-day clock and a day counter 16 for counting the 1-day clock.

  The time counter 4 counts the second clock generation circuit 12 among a plurality of counters (second clock generation circuit, second counter, minute counter, hour counter, and day counter) that sequentially divide the frequency of 32.768 kHz of the crystal unit. This is a correction target. The second clock generation circuit 12 is a 1/10 second counter that counts 0.1 seconds 10 times to generate a 1s clock, for example.

  Next, the operation of FIG. 3 will be described with reference to the flowchart of FIG.

  In the second clock generation circuit 12, a 1/10 second counter operates, and counts up by 0.1 second and generates 10 seconds when counted ten times. In step S11, the count value of the 1/10 second counter is compared with the set value. The set value 10 of the 1/10 second counter is set by the CPU 1, and increment (+1) is continued while the count value is smaller than this set value (step S12). When the count value becomes equal to the set value, the count value is set to zero (step S13), and counting is started from 1. Note that the count value of the next counter is increased simultaneously with the count value being set to zero. When the set value of the 1/10 second counter is increased or decreased under the control of the CPU 1, the number of counts changes. For example, when the set value 10 is 11, the count is increased to 11 and the carry is increased, so that the count-up can be delayed. When the set value 10 is 9, the count is increased to 9 and the carry is increased, so that the count-up can be accelerated.

  5 is a circuit diagram showing the configuration of the second clock generation circuit 12 with a correction function in FIG. 3, FIG. 6 is a circuit diagram showing the configuration of the counter operation control block 21 in FIG. 5, and FIG. 7 is a description of the operations in FIGS. FIG.

  In FIG. 5, a second clock generation circuit 12 with a correction function receives a one-minute clock, a correction request full count value setting signal, a correction frequency setting value, and a time correction count value, and outputs a time correction counter reset signal. A logic circuit 22 composed of an AND circuit and an OR circuit, to which a block 21, a count value obtained by incrementing (+1) the time correction count value, the time correction counter reset signal, and a logic signal '0' are input; The time correction counter 23 composed of a 7-bit flip-flop that outputs the time correction count value using the output signal of the circuit 22 as the D input and the 64 Hz clock as the clock input, and the time correction counter reset signal as the D input and the 64 Hz clock Is a flip-flop that outputs a 1s clock signal And it is configured to include a clock waveform shaping circuit 24 to be a.

  In FIG. 6, the counter operation control block 21 includes a correction period determination counter 31 composed of flip-flops, and a correction period determination counter 31 that uses an output signal of the logic circuit 32 as a D input and a one-minute clock as a clock input. A logic circuit 32 composed of an AND circuit and an OR circuit, to which a signal obtained by incrementing (+1) the output signal from the input signal, a full count value select signal from the comparator 33, and a logic signal '0' are input, and a correction period determination From the comparator 33 to which the output signal from the counter 31 and the correction frequency setting value are supplied as input, the selector 34 for selecting either the correction full count value or the normal full count value using the full count value selection signal, and the selector 34 The full count value and the time correction count value are supplied as inputs. And it is configured to include the over motor 35, a. The operation of FIGS. 5 and 6 will be described. When the comparator 33 compares the count value of the correction time determination counter 31 with the correction frequency setting value and the results match, the full count value select signal that is the output of the comparator 33 outputs ‘1’. Upon receipt of the signal, the correction time determination counter value returns to "0" and the count-up operation is performed again. That is, the correction time determination counter repeats the counting operation using the correction frequency setting value as the full count value, and the full count value select signal outputs ‘1’ at the period set by the correction frequency setting value. This full count value select signal is also a control signal for the selector 34, and controls whether the normal full count value or the correction full count value is selected as the full count value of the time correction counter. The correction full count value is selected while the full count value select signal is “1”. The comparator 35 compares the selected full count value with the count value of the time correction counter 23, and the result is a time correction counter reset signal. When the two match, the time correction counter reset signal becomes “1”, and the counter value of the time correction counter 23 returns to “0”. That is, the time correction counter operates at the correction full count value during the time correction period, and operates at the normal full count value during other normal operation periods. When time correction is not performed, it can be dealt with by setting the correction full count value to the normal full count value. The clock waveform shaping circuit 24 removes the hazard from the waveform including the hazard of the output of the comparator 35 and realizes a stable operation of the second counter 13.

  The timing chart of FIG. 7 will be described. Here, as an example, the operation of changing the full count value of the time correction counter 23 from 63 to 66 at intervals of 4 minutes to delay the measurement time is described. In order to perform correction at intervals of 4 minutes, 3 is set as a correction frequency setting value. This is because “0” is included in the correction period determination count value, so that a value obtained by “−1” with respect to the necessary time is set as the set value. The correction period determination counter 31 repeats the operation of returning to 0 when the count value reaches 3, and the full count value select signal that is the output of the comparator 33 is set to “1” only during the period when the count value of the correction period determination counter 31 is 3. Output. Since the correction full count value is set to 66, the time correction counter counts 4 clocks more than the normal count and then returns to “0”. That is, 1s clock is output with a delay of 4 clocks.

  Next, a time correction setting method will be described.

(1) Calculation method of necessary correction time In FIG. 8, t1 is time data based on the reference time when the time is changed last time, t2 is time data when the time change mode is entered, and t3 is after time change. Time data based on the reference time. It is assumed that the time counter 4 is operating even when the time change mode is entered.

  Therefore, the time t1 is a correct time based on the reference time, the time t2 is a time including an error timed by the time counter 4 immediately before the change is finished at the time t3, and the time t3 is a reference time. The correct time right after the change based. Since the time change is performed instantaneously, the times t2 and t3 on the actual time axis are almost the same time.

Correction time per unit time = (t3−t2) / (t2−t1) (1)
If the time t2 to be changed is ahead of the time t3 at the time of change: the clock is delayed. If the time t2 to be changed is behind the time t3 at the time of change: Advance the clock. Correction time per unit time using the above equation (1) from three values of time t1, time t2 including an error immediately before clock adjustment, and correct time t3 immediately after clock adjustment this time By calculating (advance amount or delay amount) and adjusting the counter value (set value) of the time counter 4 using the calculation result, the advance / delay state of the clock can be delayed or accelerated. It is possible to correct a time error caused by a clock error characteristic of the clock.

  In the present embodiment, since the time counter 4 is operating even when the time is set, the counter value changes at the moment when the time is switched (that is, when the adjustment is completed). On the other hand, when the time counter is stopped and the time adjustment work is performed, it is necessary to adjust the time in consideration of the work time from the work start to the work end (that is, the work time is added). Can not. In this embodiment, the time data including the error before the change and the correct time data after the change can be acquired at almost the same timing when the time is adjusted (that is, when the time is changed). Also good.

(2) Specific correction time setting method i) When correction is performed once per minute, the minimum correction time per day is 22.5 by setting the full count value of the time correction counter to 63 ± n. × n seconds / day correction is possible.

      24h × 60m × (1/64 Hz) = 22.5 seconds.

  ii) The correction time per day when correction is performed once every 10 minutes can be corrected to 2.25 × n seconds / day by setting the full count value of the time correction counter to 63 ± n.

      24 h × (60 m / 10 m) × (1/64 Hz) = 2.25 seconds.

  In this way, time correction can be performed freely by setting the correction frequency and adjusting the full count value of the time correction counter.

  Example) Here, a correction amount is obtained when t2 = t1 = 5 days and t3-t2 = 1 minute (delay error). Further, a correction full count value is obtained when the correction frequency is set to once every 10 minutes.

Correction time every 10 minutes = (n / 64) seconds Converting 5 days into 10 minutes, 5 x 24 x 60 ÷ 10 = 720 units
One correction amount = (60/720) ÷ (1/64) = 5.3
Therefore, the correction full count value = 63 + 5 = 68
According to the second embodiment described above, from the three values of the correct time when the clock was set last time, the time measured including an error immediately before the current clock was set, and the correct time immediately after the current clock was set. By calculating the amount of advance or delay per unit time and reflecting the calculation result in the counter setting value of the time counter, the counter value of the time counter is adjusted and the error based on the clock error characteristics of the watch is corrected. can do.

  The present invention can be applied to a clock, various electronic devices with a built-in clock, for example, portable devices such as electronic notebooks and mobile phones, home appliances such as VTRs and DVDs, as well as business information devices including personal computers and fax machines. It can be used widely.

1 is a block diagram illustrating a configuration of a timepiece according to a first embodiment of the invention. The flowchart which shows the operation | movement at the time of the time adjustment in the timepiece of FIG. The block diagram which shows the structure of the time counter in the timepiece of Example 2 of this invention. The flowchart explaining operation | movement of a time counter. FIG. 4 is a circuit diagram showing a configuration of a second clock generation circuit with a correction function in FIG. 3. FIG. 6 is a circuit diagram showing a configuration of a counter operation control block of FIG. 5. 7 is a flowchart for explaining the operation of FIGS. The figure explaining the calculation method of correction time.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... I / O, 4 ... Time counter, 5 ... Non-volatile memory, 6 ... LCD controller, 8 ... LCD.

Claims (4)

A time counter that measures time,
Operation means for operating time adjustment;
When a user makes a time change, a means of detecting whether the change has advanced or delayed the time,
Means for adjusting speeding up or delaying the time counting operation of the time counter according to the detected content;
After that, when the time adjustment operation is performed for the second and subsequent times, the operation contents of whether the advance operation or the delay operation has been performed is accumulated every time from the first time, and depending on the numerical value of the accumulation result Means for changing the degree of adjustment of the amount of advance or delay of the counter value of the time counter;
A watch characterized by comprising: A time counter that measures time,
Operation means for operating time adjustment;
Means for storing the time immediately after the last time adjustment;
This time, means to memorize the time just before the time,
This time, means to memorize the time immediately after the time adjustment,
Means for calculating the amount of advance or delay per unit time from these three time values;
Means for adjusting the counter value of the time counter using the amount of advance or delay per unit time;
A watch characterized by comprising: A method for adjusting an error of a clock when a user performs an operation to correct time advance or delay,
When a user makes a time change, it detects whether the change has advanced or delayed the time,
According to the detection content, adjust the time counter operation to speed up or delay,
After that, when performing the time adjustment operation for the second time and thereafter, the operation contents of whether the advance operation or the delay operation was performed is accumulated every time from the first time,
An error adjustment method for a timepiece, characterized in that the degree of adjustment of the advance amount or delay amount of the counter value of the time counter is changed according to the numerical value of the accumulated result. A method for adjusting an error of a clock when a user performs an operation to correct time advance or delay,
Remember the time immediately after the last time adjustment,
This time, memorize the time just before the time adjustment,
This time, memorize the time immediately after the time adjustment,
Calculate the amount of advance or delay per unit time from these three time values,
A method for adjusting an error of a timepiece, wherein the counter value of the time counter is adjusted using the amount of advance or delay per unit time.

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